 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| 9255e-avr-08/14 features high-performance, low-power atmel ? avr ? 8-bit microcontroller advanced risc architecture 131 powerful instructions ? mo st single-clock cycle execution 32 8 general purpose working registers fully static operation up to 16mips throughput at 16mhz on-chip 2-cycle multiplier high endurance non-volatile memory segments 16/32/64kbytes of in- system self-programmabl e flash program memory 512/1/2kbytes eeprom 1/2/4kbytes internal sram write/erase cycles: 10,0 00 flash/ 100,000 eeprom data retention: 20 years at 85c/ 100 years at 25c (1) optional boot code section with independent lock bits in-system programming by on-chip boot program true read-while-write operation programming lock for software security qtouch ? library support capacitive touch buttons, sliders and wheels qtouch and qmatrix acquisition up to 64 sense channels jtag (ieee std. 1149.1 compliant) interface boundary-scan capabilities according to the jtag standard extensive on-chip debug support programming of flash, eeprom, fuses, and lock bits through the jtag interface (1) peripheral features two 8-bit timer/counters with separate prescalers and compare modes one/two 16-bit timer/counter with sepa rate prescaler, compare mode, and capture mode real time counter with separate oscillator 1. see section 5. ?data retention? on page 8 for details. atmega164p-b/atmega324p-b/ atmega644p-b automotive 8-bit atmel microcontroller with 16/32/64kbytes in-system programmable flash datasheet
atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 2 six pwm channels 8-channel, 10-bit adc differential mode with selectable gain at 1x, 10x or 200x byte-oriented two-wire serial interface two programmable serial usart master/slave spi serial interface programmable watchdog timer with separate on-chip oscillator on-chip analog comparator interrupt and wake-up on pin change special microcontroller features power-on reset and programmable brown-out detection internal calibrated rc oscillator external and internal interrupt sources six sleep modes: idle, adc noise reduction, power-save, power-down, standby and extended standby i/o and packages 32 programmable i/o lines 44-lead tqfp, 44-pad qfn/mlf operating voltages 2.7 to 5.5v speed grades 0 to 8mhz at 2.7 to 5.5v; 0 to 16mhz at 4.5 to 5.5v power consumption at 8mhz, 2.7v, 25c active: 4.8ma idle mode: 1ma power-down mode: 0.6a 3 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 1. pin configurations 1.1 pinout - tqfp/qfn/mlf for atmega164p-b/324p-b/644p-b figure 1-1. pinout note: the large center pad underneath the qfn/mlf package should be soldered to ground on the board to ensure good mechanical stability. (pcint13/cp3/mosi) pb5 44 1 2 3 4 5 6 tqfp/qfn/mlf 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 43 42 41 40 39 38 37 36 35 34 12 13 14 15 16 17 18 19 20 21 (pcint27/txd1/int1) pd3 (pcint28/xck1/oc1b) pd4 (pcint30/oc2b/icp) pd6 (pcint29/oc1a) pd5 (pcint31/oc2a) pd7 (pcint16/scl) pc0 (pcint17/sda) pc1 (pcint18/tck) pc2 (pcint19/tms) pc3 vcc gnd (pcint15/oc3b/sck) pb7 (pcint24/rxd0/t3) pd0 (pcint25/txd0) pd1 (pcint26/rxd1/int0) pd2 reset vcc gnd xtal2 xtal1 (pcint14/oc3a/miso) pb6 pa4 (adc4/pcint4) pa5 (adc5/pcint5) pa6 (adc6/pcint6) pa7 (adc7/pcint7) pc7 (tosc2/pcint23) pc6 (tosc1/pcint22) pc5 (tdi/pcint21) pc4 (tdo/pcint20) pb2 (ain0/int2/pcint10) pb1 (t1/clko/pcint9) pb0 (xck0/t0/pcint8) pa0 (adc0/pcint0) pa1 (adc1/pcint1) pa2 (adc2/pcint2) pa3 (adc3/pcint3) gnd vcc pb4 (ss/oc0b/pcint12) pb3 (ain1/oc0a/pcint11) aref gnd avcc 22 atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 4 2. overview the atmega164p-b/324p-b/644p-b is a low-power cmos 8-bit microcontroller based on the avr ? enhanced risc architecture. by executing powerful inst ructions in a single clock cycle, the atmega164p-b/324p-b/644p-b achieves throughputs approaching 1 mips per mhz allowing the system desi gner to optimize power consumption versus processing speed. 2.1 block diagram figure 2-1. block diagram the avr core combines a rich instruction set with 32 general purpose working registers. all the 32 registers are directly connected to the arithmetic logic unit (alu), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. the resulti ng architecture is more code efficient while achieving throughputs up to ten times faster than conventional cisc microcontrollers. oscillator circuits/ clock generation power supervision por/ bod and reset watchdog timer watchdog oscillator avr cpu 16 bit t/c 3 port c (8) tosc2/pc7 tosc1/pc6 pc5 to 0 pd7 to 0 port d (8) sram flash 8 bit t/c 2 16 bit t/c 1 8 bit t/c 0 spi usart 0 usart 1 port b (8) port a (8) pa7 to 0 pa7 to 0 gnd pb7 to 0 analog comparator a/d converter internal bandgap reference twi jtag/ocd eeprom xtal1 reset xtal2 5 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 the atmega164p-b/324p-b/644p-b provide the following features: 16/32/64kbytes of in-system pr ogrammable flash with re ad-while-write capabili ties, 512/1/2kbytes eeprom, 1/2/4kbytes sram, 32 general purpose i/o lines, 32 general purpose worki ng registers, real time count er (rtc), three flexible timer/counters with compare modes and pwm, 2 usarts, a byte oriented 2-wire serial interface, a 8-channel, 10-bit adc with optional differential input stage with programmable gain, pr ogrammable watchdog timer with internal oscillator, an spi serial port, ieee std. 1149.1 compliant jtag test interfac e, also used for accessing the on-chip debug system and programming and six software selectable power saving modes . the idle mode stops the cpu while allowing the sram, timer/counters, spi port, and interrupt syst em to continue functioning. the powe r-down mode saves the register contents but freezes the oscillator, disabling all other chip functions un til the next interrupt or hardwa re reset. in power-save mode, the asynchronous timer continues to run, allowing the user to mainta in a timer base while the rest of the device is sleeping. the adc noise reduction mode stops the cpu and all i/o modules except asynchronous timer and adc, to minimize switching noise during adc conversions. in standby mode, the crystal/resona tor oscillator is running while the rest of the device is sleeping. this allows very fast start-up combined with low power consumption. in extended standby mode, both the main oscillator and the asynchronous timer continue to run. atmel ? offers the qtouch ? library for embedding capacitive touch butto ns, sliders and wheels functionality into avr microcontrollers. the patented charge-tr ansfer signal acquisition offers robust sensing and includes fully debounced reporting of touch keys and includes adjacent key suppression ? (aks ? ) technology for unambiguous detection of key events. the easy-to-use qtouch suite to olchain allows you to explore, develop and debug your own touch applications. the device is manufactured using atmel?s high-density nonvolatile memory technology. the on-chip isp flash allows the program memory to be reprogrammed in-system through an sp i serial interface, by a conventional nonvolatile memory programmer, or by an on-chip boot program running on the avr core. the boot program can use any interface to download the application program in the application flash memory. software in the boot flash section will continue to run while the application flash section is updated, providing true read-w hile-write operation. by combining an 8-bit risc cpu with in-system self-programmable flash on a monolithic chip , the atmel atmega164p-b/324p-b/644p-b is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. the atmega164p-b/324p-b/644p-b is supported with a full su ite of program and system de velopment tools including: c compilers, macro assemblers, program debugger/simulat ors, in-circuit emulators, and evaluation kits. 2.2 automotive quality grade the atmega164p-b/324p-b/644p-b have been developed and manufactured according to the most stringent requirements of the international standard iso-ts-16949. this data sheet contains limit values extracted from the results of extensive characterization (temperature and voltage). the quality and reliability of theatmega 164p-b/324p-b/644p-b have been verified during regular product qualification as per aec-q100 grade 1. as indicated in the ordering information paragraph, the pr oducts are available in on ly one temperature grade. 2.3 comparison between atmega164p-b, atmega324p-b and atmega644p-b table 2-1. temperature grade identification for automotive products temperature temperature identifier comments ?40; +125c z full automotive temperature range table 2-2. differences between atmega164p-b, atmega324p-b and atmega644p-b device flash eeprom ram unit atmega164p-b 16k 512 1k bytes atmega324p-b 32k 1k 2k atmega644p-b 64k 2k 4k atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 6 2.4 pin descriptions 2.4.1 vcc digital supply voltage. 2.4.2 gnd ground. 2.4.3 port a (pa7:pa0) port a serves as analog inputs to the analog-to-digital converter. port a also serves as an 8-bit bi-directional i/o port with inte rnal pull-up resistors (selected for each bit). the port a outp ut buffers have symmetrical drive characteristics with both high sink and source capability. as inputs, port a pins that are externally pulled low will source current if the pull-up resistors are activated. the port a pins are tri-stated when a reset condition becomes active, even if the clock is not running. port a also serves the functions of various special f eatures of the atmega164p-b/ 324p-b/644p-b as listed in section 14.3.1 ?alternate functions of port a? on page 63 . 2.4.4 port b (pb7:pb0) port b is an 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port b output buffers h ave symmetrical drive characteristics with both high sink and source capability. as inputs, port b pins that are externally pulled low will source current if the pull-up resi stors are activated. the port b pins ar e tri-stated when a reset condition becomes active, even if the clock is not running. port b also serves the functions of various special f eatures of the atmega164p-b/ 324p-b/644p-b as listed in section 14.3.2 ?alternate functions of port b? on page 65 . 2.4.5 port c (pc7:pc0) port c is an 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bi t). the port c output buffers h ave symmetrical drive characteristics with both high sink and source capability. as inputs, port c pins that are externally pulled low will source current if the pull-up resi stors are activated. the port c pins ar e tri-stated when a reset condition becomes active, even if the clock is not running. port c also serves the functions of the jtag interface, along with special features of the at mega164p-b/324p-b/644p-b as listed in section 14.3.3 ?alternate functions of port c? on page 68 . 2.4.6 port d (pd7:pd0) port d is an 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bi t). the port d output buffers h ave symmetrical drive characteristics with both high sink and source capability. as inputs, port d pins that are externally pulled low will source current if the pull-up resi stors are activated. the port d pins ar e tri-stated when a reset condition becomes active, even if the clock is not running. port d also serves the functions of various special fe atures of the atmega164p-b/3 24p-b/644p-b as listed in section 14.3.4 ?alternate functions of port d? on page 70 . 2.4.7 reset reset input. a low level on this pin for longer than the minimu m pulse length will generate a reset, even if the clock is not running. the minimum pulse length is given in section 28.5 ?system and reset characteristics? on page 291 . shorter pulses are not guaranteed to generate a reset. 2.4.8 xtal1 input to the inverting oscillator amplifier and input to the internal clock operating circuit. 7 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 2.4.9 xtal2 output from the inverting oscillator amplifier. 2.4.10 avcc avcc is the supply voltage pin for port a and the analog-to-di gital converter. it should be externally connected to v cc , even if the adc is not used. if the adc is used, it should be connected to v cc through a low-pass filter. 2.4.11 aref this is the analog reference pin for the analog-to-digital converter. atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 8 3. resources a comprehensive set of development tools, application notes and datas heetsare available for download on http://www.atmel.com/avr 4. about code examples this documentation contains simple code ex amples that briefly show how to use various parts of the device. be aware that not all c compiler vendors include bit definitions in the header files and interrupt handling in c is compiler dependent. pleas e confirm with the c compiler documentation for more details. the code examples assume that the part specific header file is included before compilation. for i/o registers located in extended i/o map, ?in?, ?out?, ?sbis?, ? sbic?, ?cbi?, and ?sbi? inst ructions must be replaced wit h instructions that allow access to extended i/o. typically ?lds? and ?sts? combined with ?sbrs?, ?sbrc?, ?sbr?, and ?cbr?. note: 1. 5. data retention reliability qualification results show that the projected data retention failure rate is much less than 1 ppm over 20 years at 85c or 100 years at 25c. 6. capacitive touch sensing the atmel qtouch library provides a simple to use solution to realize touch sensitive in terfaces on most atmel avr microcontrollers. the qtouch library includes support for the qtouch and qmatrix acquisition methods. touch sensing can be added to any application by linking the ap propriate atmel qtouch library for the avr microcontroller. this is done by using a simple set of apis to define the t ouch channels and sensors, and then calling the touch sensing api?s to retrieve the channel information and determine the touch sensor states. the qtouch library is free and downloadable from the atmel website at the following location: http://www.atmel.com/qtouchlibrary for implementation details and other information, refer to the at mel qtouch library user guide - also available for download from the atmel website. 9 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 7. avr cpu core 7.1 overview this section discusses the avr ? core architecture in general. the main function of the cpu core is to ensure correct program execution. the cpu must therefore be able to acce ss memories, perform calculations, control peripherals, and handle interrupts. figure 7-1. block diagram of the avr architecture in order to maximize performance and parallelism, the avr uses a harvard arch itecture ? with separate memories and buses for program and data. instructions in the program memo ry are executed with a single level pipelining. while one instruction is being executed, the next in struction is pre-fetched from the program memory. this co ncept enables instructions to be executed in every clock cycle. the program memory is in-system reprogrammable flash memory. the fast-access register file contains 32 x 8-bit general purpose working regi sters with a single clock cycle access time. this allows single-cycle arithmetic logic unit (alu) operation. in a typical alu operat ion, two operands are output from the register file, the oper ation is executed, and the result is stored back in th e register file ? in one clock cycle. six of the 32 registers can be used as three 16-bit indirect address register pointers for data space addressing ? enabling efficient address calculations. one of the these address pointers c an also be used as an address pointer for look up tables in flash program memory. these added function registers are the 16 -bit x-, y-, and z-register, de scribed later in this section. the alu supports arithmetic and logic operat ions between registers or between a constant and a register. single register operations can also be executed in the alu. after an arithmetic operation, the status register is updated to reflect information about the result of the operation. status and control interrupt unit 32 x 8 general purpose registers alu data bus 8-bit data sram spi unit instruction register instruction decoder watchdog timer analog comparator eeprom i/o lines i/o module n control lines direct addressing indirect addressing i/o module 2 i/o module 1 program counter flash program memory atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 10 program flow is provided by conditional and unconditional ju mp and call instructions, able to directly address the whole address space. most avr instructions have a single 16-bit wo rd format. every program memory address contains a 16 or 32-bit instruction. program flash memory space is divided in two sections, the boot program section and the applic ation program section. both sections have dedicated lock bits for write and read/write prot ection. the spm instruction that writes into the application flash memory section must reside in the boot program section. during interrupts and subroutine calls, the return address prog ram counter (pc) is stored on the stack. the stack is effectively allocated in the general data sr am, and consequently the stack size is onl y limited by the total sram size and the usage of the sram. all user programs must initialize the sp in the reset routine (before subroutines or interrupts are executed). the stack pointer (sp) is read /write accessible in the i/o space. the data sram can easily be accessed through the five different addressing modes supported in the avr architecture. the memory spaces in the avr architecture are all linear and regular memory maps. a flexible interrupt module has its control registers in the i/o space with an additional global interrupt enable bit in the st atus register. all interrupts have a separate interrupt vector in th e interrupt vector table. the interrupts have priority in accord ance with their interrupt vector position. the lower the in terrupt vector address, the higher the priority. the i/o memory space contains 64 addresses for cpu peripheral functions as control registers, spi, and other i/o functions. the i/o memory can be accessed directly, or as the data space lo cations following those of the register file, 0x20 - 0x5f. in addition, the atmega164p-b/324p-b/644p-b has extended i/ o space from 0x60 - 0xff in sram where only the st/sts/std and ld/lds/ldd instructions can be used. 7.2 alu ? arithmetic logic unit the high-performance avr alu operates in direct connection wi th all the 32 general purpose working registers. within a single clock cycle, arithmetic operations between general pu rpose registers or between a register and an immediate are executed. the alu operations are divided into three main ca tegories ? arithmetic, logica l, and bit-functions. some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. see the ?instruction set? section for a detailed description. 7.3 status register the status register contains information about the result of the most rec ently executed arithmetic instruction. this information can be used for altering program flow in order to per form conditional operations. note that the status register is updated after all alu operations, as specifi ed in the instruction set reference. this will in many cases remove the need for using the dedicated compare instructions, re sulting in faster and more compact code. the status register is not automati cally stored when entering an interrupt r outine and restored when returning from an interrupt. this must be handled by software. 7.3.1 sreg ? status register the avr status register ? sreg ? is defined as: ? bit 7 ? i: global interrupt enable the global interrupt enable bit must be set for the interrupts to be enabled. the individual interrupt enable control is then performed in separate control registers. if the global interrupt enable register is cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. the i-bi t is cleared by hardware after an interrupt has occurred, and is set by the reti instruction to enable subs equent interrupts. the i-bit can also be se t and cleared by the application with the sei and cli instructions, as describ ed in the instruction set reference. ? bit 6 ? t: bit copy storage the bit copy instructions bld (bit load) and bst (bit store) us e the t-bit as source or destination for the operated bit. a bit from a register in the register file can be copied into t by th e bst instruction, and a bit in t can be copied into a bit in a register in the register f ile by the bld instruction. bit 76543210 0x3f (0x5f) i t h s v n z c sreg read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 11 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 ? bit 5 ? h: half carry flag the half carry flag h indicates a half carry in some arithmetic operations. half carry is usef ul in bcd arithmetic. see the ?instruction set description? for detailed information. ? bit 4 ? s: sign bit, s = n v the s-bit is always an exclusive or between the negative fl ag n and the two?s complement overflow flag v. see the ?instruction set description? for detailed information. ? bit 3 ? v: two?s complement overflow flag the two?s complement overflow flag v supports two?s comple ment arithmetics. see the ?instruction set description? for detailed information. ? bit 2 ? n: negative flag the negative flag n indicates a negative result in an arithmetic or logic operation. see the ?ins truction set description? for detailed information. ? bit 1 ? z: zero flag the zero flag z indicates a zero result in an arithmetic or l ogic operation. see the ?instruction set description? for detailed information. ? bit 0 ? c: carry flag the carry flag c indicates a carry in an arithmetic or logi c operation. see the ?instruction set description? for detailed information. 7.4 general purpose register file the register file is optimized for the avr enhanced risc in struction set. in order to achieve the required performance and flexibility, the following in put/output schemes are supported by the register file: one 8-bit output operand and one 8-bit result input two 8-bit output operands and one 8-bit result input two 8-bit output operands and one 16-bit result input one 16-bit output operand an d one 16-bit result input figure 7-2 shows the structure of the 32 general purpose working registers in the cpu. figure 7-2. avr cpu general purpose working registers 7 0 addr. r0 0x00 r1 0x01 r2 0x02 ? r13 0x0d general r14 0x0e purpose r15 0x0f working r16 0x10 registers r17 0x11 ? r26 0x1a x-register low byte r27 0x1b x-register high byte r28 0x1c y-register low byte r29 0x1d y-register high byte r30 0x1e z-register low byte r31 0x1f z-register high byte atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 12 most of the instructions operating on the regi ster file have direct access to all regi sters, and most of them are single cycle instructions. as shown in figure 7-2 , each register is also assigned a data memory addr ess, mapping them directly into the first 32 locations of the user data space. although not being physically implemented as sram locations, this memory organization provides great flexibility in access of the registers, as the x- , y- and z-pointer registers can be set to index any register i n the file. 7.4.1 the x-register, y-register, and z-register the registers r26..r31 have some added functions to their general purpose usage. these registers are 16-bit address pointers for indirect addressing of the data space. the three i ndirect address registers x, y, and z are defined as described in figure 7-3 . figure 7-3. the x-, y-, and z-registers in the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instru ction set reference for details). 7.5 stack pointer the stack is mainly used for storing te mporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. note that the stack is implemented as growing from higher to lower memory locations. the stack pointer register always points to t he top of the stack. the stack pointer point s to the data sram stack area where the subroutine and interr upt stacks are located. a stack push command will decrease the stack pointer. the stack in the data sram must be def ined by the program before any subroutin e calls are executed or interrupts are enabled. initial stack pointer value equals the last address of the internal sram and the stack pointer must be set to point above start of the sram, see figure 8-2 on page 17 . see table 7-1 for stack pointer details. the avr stack pointer is implemented as two 8-bit register s in the i/o space. the number of bits actually used is implementation dependent, see table 7-2 on page 13 . note that the data space in some implementations of the avr architecture is so small that only spl is needed. in this case, the sph register will not be present. 15 xh xl 0 x-register 7 0 7 0 r27 (0x1b) r26 (0x1a) 15 yh yl 0 y-register 7 0 7 0 r29 (0x1d) r28 (0x1c) 15 zh zl 0 z-register 7 0 7 0 r31 (0x1f) r30 (0x1e) table 7-1. stack pointer instructions instruction stack pointer description push decremented by 1 data is pushed onto the stack call icall rcall decremented by 2 return address is pushed onto the st ack with a subroutine call or interrupt pop incremented by 1 data is popped from the stack ret reti incremented by 2 return address is popped from the stack wi th return from subroutine or return from interrupt 13 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 7.5.1 sph and spl ? stack pointer high and stack pointer low note: 1. initial values respectively for the atmega164p-b/324p-b/644p-b 7.6 instruction execution timing this section describes the general access timing concepts fo r instruction execution. the avr cpu is driven by the cpu clock clk cpu , directly generated from the selected clock source for the chip. no internal clock division is used. figure 7-4 on page 13 shows the parallel instruction fetches and instructio n executions enabled by the harvard architecture and the fast-access register file concept. this is the basic pipelining concept to obtain up to 1mips per mhz with the corresponding unique results for f unctions per cost, functions per cl ocks, and functions per power-unit. figure 7-4. the parallel instructio n fetches and instruction executions bit 151413121110 9 8 0x3e (0x5e) ? ? ? sp12 sp11 sp10 sp9 sp8 sph 0x3d (0x5d) sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 spl 76543210 read/write r r r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0/1 () 0/1 () 1/0 () 00 11111111 table 7-2. stack pointer size device stack pointer size atmega164p-b sp[10:0] atmega324p-b sp[11:0] atmega644p-b sp[12:0] clk cpu 1st instruction fetch 1st instruction execute 2nd instruction fetch t1 t2 t3 t4 2nd instruction execute 3rd instruction fetch 3rd instruction execute 4th instruction fetch atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 14 figure 7-5 shows the internal timing concept for the register file. in a single clock cycle an alu operation using two register operands is executed, and the result is stored back to the destination register. figure 7-5. single cycle alu operation 7.7 reset and interrupt handling the avr provides several different interrupt sources. these interrupts and the separate reset vector each have a separate program vector in the program memory sp ace. all interrupts are assigned individual enable bits which must be written logic one together with the global interrupt enable bit in the status register in order to enable the interrupt. depending on the program counter value, interrupts may be automatically disabled when boot lock bits blb02 or blb12 are programmed. this feature improves software security. see section 27. ?memory programming? on page 255 for details. the lowest addresses in the program memory space are by default defined as the re set and interrupt vect ors. the complete list of vectors is shown in section 12. ?interrupts? on page 49 . the list also determines the prio rity levels of the different interrupts. the lower the addres s the higher is the priority level. reset has the highest priority, and next is int0 ? the external interrupt request 0. the interrupt vectors can be moved to the start of the boot flas h section by setting the ivsel bit in the mcu control register (mcucr). refer to section 12. ?interrupts? on page 49 for more information . the reset vector can also be moved to the start of the boot flash section by pr ogramming the bootrst fuse, see section 27. ?memory programming? on page 255 . when an interrupt occurs, the global interrupt enable i-bit is cl eared and all interrupts are disabled. the user software can write logic one to the i-bit to enable nested interrupts. all enab led interrupts can then interrupt the current interrupt routi ne. the i-bit is automatically set when a return fr om interrupt instruction ? reti ? is executed. there are basically two types of interrupts. the first type is triggered by an event that sets the interrupt flag. for these interrupts, the program counter is vectored to the actual interr upt vector in order to execute the interrupt handling routine, and hardware clears the corresponding interrupt flag. interrupt flags can also be cleared by writing a logic one to the flag bi t position(s) to be cleared. if an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the interr upt flag will be set and remembered until the inte rrupt is enabled, or the flag is cleared by software. similarly, if one or more interrupt conditions occur while the global interrupt enable bit is cleared, the corresponding interrupt flag(s) will be set an d remembered until the global interrupt enable bit is se t, and will then be executed by order of priority. the second type of interrupts will trigger as long as the interr upt condition is present. these interrupts do not necessarily have interrupt flags. if the interrupt condition disappears befo re the interrupt is enabled, the interrupt will not be triggere d. when the avr exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served. note that the status regi ster is not automatically stored when entering an in terrupt routine, nor restored when returning from an interrupt routine. this must be handled by software. when using the cli instruction to disable interrupts, the inte rrupts will be immediately disabled. no interrupt will be execute d after the cli instruction, even if it occu rs simultaneously with the cli instruction. the following example shows how this can be used to avoid interrupts during the timed eeprom write sequence. clk cpu t1 register operands fetch result write back alu operation execute total execution time t2 t3 t4 15 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 when using the sei instruction to enable interrupts, the in struction following sei will be executed before any pending interrupts, as shown in this example. 7.7.1 interrupt response time the interrupt execution response fo r all the enabled avr interrupts is five clo ck cycles minimum. after five clock cycles the program vector address for the actual interrupt handling rout ine is executed. during these five clock cycle period, the program counter is pushed onto the stack. the vector is norma lly a jump to the interrupt routine, and this jump takes three clock cycles. if an interrupt occurs during execution of a mu lti-cycle instruction, this inst ruction is comp leted before the interrupt is served. if an interrupt occurs when the mcu is in sleep mode, the interrupt execut ion response time is increased by five clock cycles. this increase comes in addition to the start-up ti me from the sele cted sleep mode. a return from an interrupt ha ndling routine takes five clock cycles. during these five clock cycles, the program counter (three bytes) is popped back from the stack, the stack pointer is incremented by three, and the i-bit in sreg is set. assembly code example in r16, sreg ; store sreg value cli ; disable interrupts during timed sequence sbi eecr, eempe ; start eeprom write sbi eecr, eepe out sreg, r16 ; restore sreg value (i-bit) c code example char csreg; csreg = sreg; /* store sreg value */ /* disable interrupts during timed sequence */ __disable_interrupt(); eecr |= (1< 17 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 8.3 sram data memory figure 8-2 shows how the atmega164p-b/324p-b/ 644p-b sram memory is organized. the atmega164p-b/324p-b/644p-b is a co mplex microcontroller with more peripher al units than can be supported within the 64 location reserved in the opcode for the in and out instructions. for the extended i/o space from $060 - $ff in sram, only the st/sts/std and ld/lds/ldd instructions can be used. the first 4,352 data memory locations addr ess both the register file, the i/o memory , extended i/o memory, and the internal data sram. the first 32 locations address the register file, the next 64 location the standard i/o memory, then 160 locations of extended i/o memory and the next 4,096 locations address the internal data sram. the five different addressing modes for the data memory cover: direct, indirect with displacement , indirect, indirect with pre- decrement, and indirect with post-increment. in the register file , registers r26 to r31 feature the indirect addressing pointer registers. the direct addressing reaches the entire data space. the indirect with displacement mode reaches 63 address locati ons from the base address given by the y- or z-register. when using register indirect addressing modes with automatic pre-decrement and post-increment, the address registers x, y, and z are decremented or incremented. the 32 general purpose working registers, 64 i/o register s, 160 extended i/o registers and the 1024/2048/4096 bytes of internal data sram in the atmega164p-b/324p-b/644p-b are al l accessible through all these addressing modes. the register file is described in section 7.4 ?general purpose register file? on page 11 . figure 8-2. data memory map for atmega164p-b/324p-b/644p-b 8.3.1 data memory access times this section describes the general access timing concepts for internal memory access. the in ternal data sram access is performed in two clk cpu cycles as described in figure 8-3 . figure 8-3. on-chip data sram access cycles 32 registers 0x0000 0x0020 0x0060 0x0100 0x04ff/0x08ff/0x10ff 64 i/o registers 160 ext i/o registers internal sram (1024/2048/4096 *8) clk cpu t1 data data rd wr address valid compute address next instruction write read memory access instruction address t2 t3 atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 18 8.4 eeprom data memory the atmega164p-b/324p-b/644p-b contains 512/1/2kbytes of data eeprom memory. it is organized as a separate data space, in which single bytes can be read and written. th e eeprom has an endurance of at least 100,000 write/erase cycles. the access between the eeprom and the cpu is described in the fo llowing, specifyi ng the eeprom address registers, the eeprom data register , and the eeprom control register. for a detailed description of spi, jtag and parallel data downloading to the eeprom, see section 27.6 ?parallel programming parameters, pin mapping, and commands? on page 259 , section 27.8 ?serial downloading? on page 270 , and section 27.10 ?programming via the jtag interface? on page 274 respectively. 8.4.1 eeprom read/write access the eeprom access registers are a ccessible in the i/o space. see section 8.6 ?register description? on page 19 for details. the write access time for the eeprom is given in table 8-2 on page 21 . a self-timing function, however, lets the user software detect when the next byte can be written. if the us er code contains instructions that write the eeprom, some precautions must be taken. in h eavily filtered power supplies, v cc is likely to rise or fall slowly on power-up/down. this causes the device for some period of time to run at a volt age lower than specified as minimum for the clock frequency used. see section 8.4.2 ?preventing eepr om corruption? on page 18 for details on how to avoid problems in these situations. in order to prevent unint entional eeprom writes, a specific wr ite procedure must be followed. refer to the descrip tion of the eeprom control register for details on this. when the eeprom is read, the cpu is halted for four clock cycles before the next instru ction is executed. when the eeprom is written, the cpu is ha lted for two clock cycles before the next instruction is executed. 8.4.2 preventing eeprom corruption during periods of low v cc, the eeprom data can be corrupted because the su pply voltage is too low for the cpu and the eeprom to operate properly. these issues are the same as for board level systems using eeprom, and the same design solutions should be applied. an eeprom data corruption can be caused by two situations when the voltage is too low. first, a regu lar write sequence to the eeprom requires a minimum vo ltage to operate correct ly. secondly, the cpu itself can ex ecute instructions incorrectly, if the supply voltage is too low. eeprom data corruption can easily be avoided by following this design recommendation: keep the avr reset active (low) during periods of insufficie nt power supply voltage. this can be done by enabling the internal brown-out detector (bod). if th e detection level of the internal bod does not match the needed detection level, an external low v cc reset protection circuit can be used. if a reset occu rs while a write operation is in progress, the write operation will be completed provided that the power supply voltage is sufficient. 8.5 i/o memory the i/o space definition of the atme ga164p-b/324p-b/644p-b is shown in section 30. ?register summary? on page 323 . all atmega164p-b/324p-b/644p-b i/os and peripherals are placed in the i/o space. all i/o locations may be accessed by the ld/lds/ldd and st/sts/std instructions, transferring data between the 32 general purpose working registers and the i/o space. i/o registers within the address range 0x00 - 0x1f ar e directly bit-accessible using the sbi and cbi instructions. in these registers, the value of single bits can be checked by using the sbis and sbic instruct ions. refer to the instruction set section for more details. when using the i/o specific co mmands in and out, the i/o addresses 0x00 - 0x3f must be used. when addressing i/o registers as data space using ld and st instructions, 0x20 must be added to these addresses. the atmega164p-b/324p-b/644p-b is a co mplex microcontroller with more peripher al units than can be supported within the 64 location reserved in opcode for the in and out instru ctions. for the extended i/o sp ace from 0x60 - 0xff in sram, only the st/sts/std and ld/lds/ldd instructions can be used. for compatibility with future devices, reserved bits should be wr itten to zero if accessed. re served i/o memory addresses should never be written. some of the status flags are cleared by writing a logical one to them. note tha t, unlike most other avrs, the cbi and sbi instructions will only operate on the spec ified bit, and can therefore be used on registers containing such status flags. the cbi and sbi instructions work wit h registers 0x00 to 0x1f only. the i/o and peripherals control registers are explained in later sections. 19 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 the atmega164p-b/324p-b/644p-b contains three general pu rpose i/o registers, see section 8.6 ?register description? on page 19 . these registers can be used for storing any information, and they are particularly useful for storing global variables and status flags. genera l purpose i/o registers within the address range 0x 00 - 0x1f are directly bit-accessible using the sbi, cbi, sbis, and sbic instructions. 8.6 register description 8.6.1 eearh and eearl ? the eeprom address register ? bits 15:12 ? reserved these bits are reserved bits in the atmega164p- b/324p-b/644p-b and will always read as zero. ? bits 11:0 ? eear8:0: eeprom address the eeprom address register s ? eearh and eearl specify the eeprom address in the 512 /1k/2kbytes eeprom space. the eeprom data bytes are addressed linearly be tween 0 and 511/1023/2047. the initial value of eear is undefined. a proper va lue must be written before the eeprom may be accessed. 8.6.2 eedr ? the eeprom data register ? bits 7:0 ? eedr7:0: eeprom data for the eeprom write operation, the eedr register contains th e data to be written to the eepr om in the address given by the eear register. for the eeprom read operation, the ee dr contains the data read out from the eeprom at the address given by eear. 8.6.3 eecr ? the eeprom control register ? bits 7:6 ? reserved these bits are reserved bits in the atmega164p- b/324p-b/644p-b and will always read as zero. ? bits 5:4 ? eepm1 and eepm0: eeprom programming mode bits the eeprom programming mode bit setting defines which programming action that will be triggered when writing eepe. it is possible to program data in one atomic operation (erase the old value and program the new val ue) or to split the erase and write operations in two di fferent operations. the programming times for the different modes are shown in table 8-1 on page 20 . while eepe is set, any write to eepmn will be ignored. during reset, the eepmn bits will be reset to 0b00 unless the eeprom is busy programming. bit 15 14 13 12 11 10 9 8 0x22 (0x42) ? ? ? ? eear11 eear10 eear9 eear8 eearh 0x21 (0x41) eear7 eear6 eear5 eear4 eear3 eear2 eear1 eear0 eearl 7654 3 2 10 read/write r r r r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 x x x x xxxx x x xx bit 76543210 0x20 (0x40) msb lsb eedr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 0x1f (0x3f) ? ? eepm1 eepm0 eerie eempe eepe eere eecr read/write r r r/w r/w r/w r/w r/w r/w initial value 0 0 x x 0 0 x 0 atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 20 ? bit 3 ? eerie: eeprom ready interrupt enable writing eerie to one enables the eeprom ready interrupt if the i bit in sreg is set. writin g eerie to zero disables the interrupt. the eeprom re ady interrupt generates a constant interrupt when eepe is cleared. ? bit 2 ? eempe: eeprom master programming enable the eempe bit determines whethe r setting eepe to one causes the eeprom to be written. when eempe is set, setting eepe within four clock cycles will write data to the eeprom at the selected add ress if eempe is zero, setting eepe will have no effect. when eempe has been written to one by software, hardware clears the bit to zero after four clock cycles. see the description of the eepe bi t for an eeprom write procedure. ? bit 1 ? eepe: eeprom programming enable the eeprom write enable signal eepe is the write strobe to the eeprom. when address and data are correctly set up, the eepe bit must be written to one to write the value into the eeprom. the eempe bit must be written to one before a logical one is written to eepe, otherwise no eeprom write ta kes place. the following procedure should be followed when writing the eeprom (the order of steps 3 and 4 is not essential): 1. wait until eepe becomes zero. 2. wait until spmen in spmcsr becomes zero. 3. write new eeprom address to eear (optional). 4. write new eeprom data to eedr (optional). 5. write a logical one to the eempe bit while writing a zero to eepe in eecr. 6. within four clock cycles after setti ng eempe, write a logical one to eepe. the eeprom can not be programmed during a cpu write to the flash memory. the software must check that the flash programming is completed before initiating a new eeprom write. step 2 is only relevant if t he software contains a boot loader allowing the cpu to program the flash. if the flash is never being updated by the cpu, step 2 can be omitted. see section 27. ?memory programming? on page 255 for details about boot programming. caution: an interrupt between step 5 and step 6 will make the write cycle fail, since the eeprom master write enable will time-out. if an in terrupt routine accessing the eeprom is interrupting anothe r eeprom access, the eear or eedr register will be modified, causing the interrupted eeprom access to fail. it is recommended to have the global interrupt flag cleared during all the steps to avoid these problems. when the write access time has elapsed, the eepe bit is cleared by hardware. the user software can poll this bit and wait for a zero before wr iting the next byte. when eepe has be en set, the cpu is halted for two cycles before the ne xt instruction is executed. ? bit 0 ? eere: eeprom read enable the eeprom read enable signal eere is the read strobe to t he eeprom. when the correct address is set up in the eear register, the eere bit must be written to a logic one to trigger the eeprom read. the eeprom read access takes one instruction, and the reques ted data is available immediately. when the eeprom is read, the cpu is halted for four cycles before the next instru ction is executed. the user should poll the eepe bit before starting the read operatio n. if a write operation is in progress, it is neither possib le to read the eeprom, nor to change the eear register. the calibrated oscillator is used to time the eeprom accesses. table 8-2 on page 21 lists the typical programming time for eeprom access from the cpu. table 8-1. eeprom mode bits eepm1 eepm0 programming time operation 0 0 3.4ms erase and write in one o peration (atomic operation) 0 1 1.8ms erase only 1 0 1.8ms write only 1 1 ? reserved for future use 21 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 the following code examples show one assembly and one c functi on for writing to the eeprom . the examples assume that interrupts are controlled (e.g. by disabling interrupts globa lly) so that no interrupts will occur during execution of the se functions. the examples also assume that no flash boot loader is present in the software. if such code is present, the eeprom write function must also wait for any ongoing spm command to finish. note: 1. see section 4. ?about code examples? on page 8 . table 8-2. eeprom programming time symbol number of calibrated rc oscillator cycles typical programming time eeprom write (from cpu) 26,368 3.3ms assembly code example (1) eeprom_write: ; wait for completion of previous write sbic eecr,eepe rjmp eeprom_write ; set up address (r18:r17) in address register out eearh, r18 out eearl, r17 ; write data (r16) to data register out eedr,r16 ; write logical one to eempe sbi eecr,eempe ; start eeprom write by setting eepe sbi eecr,eepe ret c code example (1) void eeprom_write( unsigned int uiaddress, unsigned char ucdata) { /* wait for completion of previous write */ while(eecr & (1< atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 24 9.1.3 flash clock ? clk flash the flash clock controls operation of the flash interface. the flash clock is usually active simultaneously with the cpu clock. 9.1.4 asynchronous timer clock ? clk asy the asynchronous timer clock allows the asynchronous timer/count er to be clocked directly from an external clock or an external 32khz clock crystal. the dedicated clock domain allo ws using this timer/counter as a real-time counter even when the device is in sleep mode. 9.1.5 adc clock ? clk adc the adc is provided with a dedicated clock do main. this allows halting the cpu and i/o clocks in order to reduce noise generated by digital circuitry. this give s more accurate adc conversion results. 9.2 clock sources the device has the following clock source options, selectable by flash fuse bits as shown below. the clock from the selected source is input to the avr clock gene rator, and routed to the appropriate modules. note: 1. for all fuses ?1? means unprogrammed while ?0? means programmed. 9.2.1 default clock source the device is shipped with internal rc osc illator at 8.0mhz and with the fuse ck div8 programmed, resulting in 1.0mhz system clock. the startup ti me is set to maximum and time-out pe riod enabled. (cksel = ?0010?, sut = ?10?, ckdiv8 = ?0?). the default setting ensures t hat all users can make their desired cl ock source setting using any available programming interface. table 9-1. device clocking options select (1) device clocking option cksel3..0 low power crystal oscillator 1111 - 1000 full swing crystal oscillator 0111 - 0110 low frequency crystal oscillator 0101 - 0100 internal 128khz rc oscillator 0011 calibrated internal rc oscillator 0010 external clock 0000 reserved 0001 25 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 9.2.2 clock startup sequence any clock source needs a sufficient v cc to start oscillating and a minimum number of oscillating cycles before it can be considered stable. to ensure sufficient v cc , the device issues an internal reset with a time-out delay (t tout ) after the device reset is released by all other reset sources. section 10.11.7 ?on-chip debug system? on page 37 describes the start conditions for the internal reset. the delay (t tout ) is timed from the watchdog oscillator and the number of cycles in the delay is set by the sutx and ckselx fuse bits. the sele ctable delays are shown in table 9-2 . the frequency of the watchdog oscillator is voltage dependent as shown in section 29. ?typical characteristics? on page 297 . main purpose of the delay is to keep the avr in reset until it is supplied with minimum vcc. the delay will not monitor the actual voltage and it will be required to select a delay longer th an the vcc rise time. if this is not possible, an internal or external brown-out detection circuit should be used. a bod circ uit will ensure sufficient vcc before it releases the reset, and the time-out delay can be disabled. dis abling the time-out delay without utilizin g a brown-out detection circuit is not recommended. the oscillator is required to oscillate for a minimum number of cycles before the clock is considered stable. an internal rippl e counter monitors the oscillator output clock, and keeps the internal reset active for a given number of clock cycles. the reset is then released and the device will start to execute. the re commended oscillator start-up time is dependent on the clock type, and varies from 6 cycles for an externally applied clock to 32kcycles for a low frequency crystal. the start-up sequence for the clock includes both the time-out delay and the start-up time wh en the device starts up from reset. when starting up from power-save or power-down mode, vcc is assumed to be at a sufficient level and only the start- up time is included. 9.2.3 clock source connections the pins xtal1 and xtal2 are input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in figure 9-2 on page 25 . either a quartz crystal or a ceramic resonator may be used. c1 and c2 should always be equal for both crystals and res onators. the optimal value of the capacitors depends on the crystal or resonator in use, th e amount of stray capacitance, and the electromagnetic noise of the environment. for ceramic resonators, the capacitor values giv en by the manufacturer should be used. figure 9-2. crystal oscillator connections table 9-2. number of watc hdog oscillator cycles typical time-out (v cc = 5.0v) typical time-out (v cc = 3.0v) number of cycles 0ms 0ms 0 4.1ms 4.3ms 512 65ms 69ms 8k (8,192) c2 xtal2 xtal1 gnd c1 atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 26 9.3 low power crystal oscillator this crystal oscillator is a low power oscillator, with reduc ed voltage swing on the xtal2 output. it gives the lowest power consumption, but is not capable of driving other clock inputs, and may be more susceptible to noise in noisy environments. in these cases, refer to section 9.4 ?full swing crystal oscillator? on page 27 . some initial guidelines for choosing capacitors for use with crystals are given in table 9-3 . the crystal should be connected as described in section 9.2.3 ?clock source connections? on page 25 . the low power oscillator can operate in three different modes, eac h optimized for a specific fr equency range. the operating mode is selected by the fuses cksel3..1 as shown in table 9-3 . notes: 1. if the crystal frequency exceeds t he specification of th e device (depends on v cc ), the ckdiv8 fuse can be pro- grammed in order to divide the internal frequency by 8. it must be ensured that the resulting divided clock meets the frequency specif ication of the device. 2. this is the recommended cksel settings for the different frequency ranges. 3. this option should not be used with crystals, only with ceramic resonators. the cksel0 fuse together with the sut1..0 fuses select the start-up times as shown in table 9-4 . table 9-3. low power crystal oscillator operating modes (1) frequency range (mhz) cksel3..1 (2) recommended range for capacitors c1 and c2 (pf) 0.4 - 0.9 100 (3) ? 0.9 - 3.0 101 12 - 22 3.0 - 8.0 110 12 - 22 8.0 - 16.0 111 12 - 22 table 9-4. start-up times for the low po wer crystal oscillator clock selection oscillator source / power conditions start-up time from power- down and power-save additional delay from reset (v cc = 5.0v) cksel0 sut1..0 ceramic resonator, fast rising power 258 ck 14ck + 4.1ms (1) 0 00 ceramic resonator, slowly rising power 258 ck 14ck + 65ms (1) 0 01 ceramic resonator, bod enabled 1k ck 14ck (2) 0 10 ceramic resonator, fast rising power 1k ck 14ck + 4.1ms (2) 0 11 ceramic resonator, slowly rising power 1k ck 14ck + 65ms (2) 1 00 crystal oscillator, bod enabled 16k ck 14ck 1 01 crystal oscillator, fast rising power 16k ck 14ck + 4.1ms 1 10 crystal oscillator, slowly rising power 16k ck 14ck + 65ms 1 11 notes: 1. these options should only be used when not operat ing close to the maximum frequency of the device, and only if frequency stability at start-up is not important for the application. these options are not suitable for crystals. 2. these options are intended for use with ceramic res onators and will ensure frequency stability at start-up. they can also be used with crystals when not operatin g close to the maximum frequency of the device, and if frequency stability at start-up is not important for the application. 27 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 9.4 full swing crystal oscillator this crystal oscillator is a full swing oscillator, with rail- to-rail swing on the xtal2 output. this is useful for driving oth er clock inputs and in noisy environments. the current consumption is higher than the low power crystal oscillator in section 9.3 on page 26 . note that the full swing crystal oscillat or will only operate for vcc = 2.7 to 5.5v. some initial guidelines for choosing capacitors for use with crystals are given in table 9-6 . the crystal should be connected as described in section 9.2.3 ?clock source connections? on page 25 . the operating mode is selected by the fuses cksel3..1 as shown in table 9-5 . notes: 1. these options should only be used when not opera ting close to the maximum frequency of the device, and only if frequency stability at start- up is not important for t he application. these options are not suitable for crystals. 2. these options are intended for use with ceramic resonator s and will ensure frequency st ability at start-up. they can also be used with crystals when not operating clos e to the maximum frequency of the device, and if fre- quency stability at start-up is not important for the application. table 9-5. full swing crystal oscillator operating modes frequency range (1) (mhz) cksel3..1 recommended range for capacitors c1 and c2 (pf) 0.4 - 16 011 12 - 22 notes: 1. if the crystal frequency exceeds the specification of the device (depends on v cc ), the ckdiv8 fuse can be programmed in order to divide the internal frequency by 8. it must be ensured that the resulting divided clock meets the frequency specification of the device. table 9-6. start-up times for the full sw ing crystal oscillator clock selection oscillator source / power conditions start-up time from power- down and power-save additional delay from reset (v cc = 5.0v) cksel0 sut1..0 ceramic resonator, fast rising power 258 ck 14ck + 4.1ms (1) 0 00 ceramic resonator, slowly rising power 258 ck 14ck + 65ms (1) 0 01 ceramic resonator, bod enabled 1k ck 14ck (2) 0 10 ceramic resonator, fast rising power 1k ck 14ck + 4.1ms (2) 0 11 ceramic resonator, slowly rising power 1k ck 14ck + 65ms (2) 1 00 crystal oscillator, bod enabled 16k ck 14ck 1 01 crystal oscillator, fast rising power 16k ck 14ck + 4.1ms 1 10 crystal oscillator, slowly rising power 16k ck 14ck + 65ms 1 11 atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 28 9.5 low frequency crystal oscillator the low-frequency crystal oscillator is optimized for use wi th a 32.768khz watch crystal. when selecting crystals, load capasitance and crystal?s equivalent series resistance, esr must be taken into consid eration. both values are specified by the crystal vendor. atmega164p-b /324p-b/644p-b oscillator is optimized for ve ry low power consumption, and thus when selecting crystals, see table 9-7 on page 28 for maximum esr recommendations on 9pf and 12.5pf crystals. note: 1. maximum esr is typical value based on characterization the low-frequency crystal oscillator provid es an internal load capacitance, see table on page 28 at each tosc pin. the capacitance (ce + ci) needed at each tosc pin can be calculated by using: where: ce - is optional external capacitors as described in figure 9-2 on page 25 ci - is the pin capacitance in table 9-8 on page 28 cl - is the load capacitance for a 32.768khz crystal specified by the crystal vendor. c s - is the total stray capacitance for one tosc pin. crystals specifying load capacitance (cl) higher than the ones given in the table 9-8 on page 28 , require external capacitors applied as described in figure 9-2 on page 25 . figure 9-3. crystal oscillator connections crystals specifying load capacitance (cl) higher than listed in table 9-8 on page 28 , require external capacitors applied as described in figure 9-2 on page 25 . to find suitable load capacitance for a 32.768k hz crysal, please consult the crystal datasheet. table 9-7. maximum esr recommendation for 32.768khz watch crystal crystal cl (pf) max esr [k ] (1) 9.0 65 12.5 30 table 9-8. capacitance for low-frequency oscillator device 32khz osc. type cap (xtal1/tosc1) cap (xtal2/tosc2) atmega164p-b/324p-b/644p-b system osc. 18pf 8pf timer osc. 6pf 6pf ce ci + 2 cl ? c s ? = 29 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 when this oscillator is selected, start-up times ar e determined by the sut fuses and cksel0 as shown in table 9-9 . 9.6 calibrated internal rc oscillator by default, the internal rc oscillator provides an approximate 8mhz clock. th ough voltage and temperature dependent, this clock can be very accurately calibrated by the user. see table 28-3 on page 290 and section 29.1.8 ?internal oscillator speed? on page 304 and section 29.2.8 ?internal oscillator speed? on page 312 for more details. the device is shipped with the ckdiv8 fuse programmed. see section 9.11 ?system clock prescaler? on page 31 for more details. this clock may be selected as t he system clock by programming the cksel fuses as shown in table 9-10 . if selected, it will operate with no external components. during reset, hardware load s the pre-programmed default 3v calibration value into the osccal register and thereby automa tically calibrates the rc oscillator for 3v op eration. if the device is to be used at 5v then the alternate rc oscillator 5v calibration byte ( table 26-5 on page 248 ) can be read from signature row and stored into the osccal register by the user application program for better 5v frequency accuracy. the accuracy of this calibration is shown as factory calibration in table 28-3 on page 290 . by changing the osccal register from sw, see section 9.12.1 ?osccal ? oscillator calibration register? on page 32 , it is possible to get a higher calibration accuracy than by using the fa ctory calibration. the accuracy of this calibration is shown as user calibration in table 28-3 on page 290 . when this oscillator is used as the chip clock, the watchdog oscillator will still be used for the watchdog timer and for the reset time-out. for more in formation on the pre-programmed calibration value, see section 27.4 ?calibration byte? on page 258 . when this oscillator is selected, start-up times are determined by the sut fuses as shown in table 9-11 on page 30 . table 9-9. start-up times for the low freq uency crystal oscillator clock selection power conditions start-up time from power- down and power-save additional delay from reset (v cc = 5.0v) cksel0 sut1..0 bod enabled 1k ck 14ck (1) 0 00 fast rising power 1k ck 14ck + 4.1ms (1) 0 01 slowly rising power 1k ck 14ck + 65ms (1) 0 10 reserved 0 11 bod enabled 32k ck 14ck 1 00 fast rising power 32k ck 14ck + 4.1ms 1 01 slowly rising power 32k ck 14ck + 65ms 1 10 reserved 1 11 note: 1. these options should only be used if frequency stability at start-up is not important for the application. table 9-10. internal calibrated rc oscillator operating modes frequency range (2) (mhz) cksel3..0 7.3 - 8.1 0010 (1) notes: 1. the device is shipped with this option selected. 2. if 8mhz frequency exceeds the specif ication of the device (depends on v cc ), the ckdiv8 fuse can be pro- grammed in order to divide the internal frequency by 8. atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 30 9.7 128khz internal oscillator the 128khz internal oscillator is a low power oscillator pr oviding a clock of 128khz. the frequency is nominal at 3v and 25c. this clock may be select as th e system clock by programming the c ksel fuses to ?00 11? as shown in table 9-12 . note: 1. note that the 128khz oscillator is a very low pow er clock source, and is not designed for high accuracy. when this clock source is selected, start-up ti mes are determined by the sut fuses as shown in table 9-13 . 9.8 external clock to drive the device from an external clock source, xtal1 should be driven as shown in figure 9-4 . to run the device on an external clock, the cksel fuses must be programmed to ?0000?. figure 9-4. external clock drive configuration table 9-11. start-up times for the internal calibrated rc oscillator clock selection power conditions start-up time from power-down and power-save additional dela y from reset (v cc = 5.0v) sut1..0 bod enabled 6 ck 14ck 00 fast rising power 6 ck 14ck + 4.1ms 01 slowly rising power 6 ck 14ck + 65ms 10 (1) reserved 11 note: 1. the device is shipped with this option selected. table 9-12. 128khz internal oscillator operating modes (2) nominal frequency cksel3..0 128khz 0011 table 9-13. start-up times for th e 128khz internal oscillator power conditions start-up time from power-down and power-save additional delay from reset sut1..0 bod enabled 6 ck 14ck 00 fast rising power 6 ck 14ck + 4ms 01 slowly rising power 6 ck 14ck + 64ms 10 reserved 11 xtal2 xtal1 gnd nc external clock signal 31 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 when this clock source is selected, start-up ti mes are determined by the sut fuses as shown in table 9-15 . when applying an external clock, it is required to avoid s udden changes in the applied clock frequency to ensure stable operation of the mcu. a variati on in frequency of more than 2% from one clock cycle to the ne xt can lead to unpredictable behavior. if changes of more than 2% is required, ensur e that the mcu is kept in reset during the changes. note that the system clock prescaler can be used to implement run-time changes of the internal clock frequency while still ensuring stable operation. refer to section 9.11 ?system clock prescaler? on page 31 for details. 9.9 timer/counter oscillator atmega164p-b/324p-b/644p-b uses the sa me type of crystal oscillator for low-frequency crystal oscillator and timer/counter oscillator. see section 9.5 ?low frequency crystal oscillator? on page 28 for details on the oscillator and crystal requirements. the device can operate its timer/counte r2 from an external 32.768khz watch crystal or a external clock source. see section 9.2.3 ?clock source connections? on page 25 for details. applying an external clock s ource to tosc1 can be done if extclk in the assr register is written to logic one. see section 17.11.4 ?ocr2a ? output compare register a? on page 136 for further descripti on on selecting external clock as input instead of a 32.768khz watch crystal. 9.10 clock output buffer the device can output the system clock on the clko pin. to enable the output, the ckout fuse has to be programmed. this mode is suitable wh en the chip clock is used to driv e other circuits on the system. the clock also will be output during reset, and the normal operation of i/o pin will be overridden w hen the fuse is programmed. any clock source, including the internal rc oscillator, can be selected when the clock is out put on clko. if the system clock prescaler is used, it is the divided system clock that is output. 9.11 system clock prescaler the atmega164p-b/324p-b/644p-b has a system clock prescaler, and the system clock can be divided by setting the section 9.12.2 ?clkpr ? clock prescale register? on page 32 . this feature can be used to decrease the system clock frequency and the power consumption when the requirement for processing power is low. this can be used with all clock source options, and it will affect the clock frequency of the cpu and all synchronous peripherals. clk i/o , clk adc , clk cpu , and clk flash are divided by a factor as shown in table 9-16 on page 33 . when switching between pr escaler settings, the system clock prescaler ensures that no glitches occurs in the clock system. it also ensures that no intermediate frequency is higher t han neither the clock frequency corresponding to the previous setting, nor the clock frequency corresponding to the new setting. table 9-14. crystal oscillator clock frequency nominal frequency cksel3..0 0 - 16mhz 0000 table 9-15. start-up times for th e external clock selection power conditions start-up time from power-down and power-save additional delay from reset (v cc = 5.0v) sut1..0 bod enabled 6 ck 14ck 00 fast rising power 6 ck 14ck + 4.1ms 01 slowly rising power 6 ck 14ck + 65ms 10 reserved 11 atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 32 the ripple counter that implements the prescaler runs at the fr equency of the undivided clock, which may be faster than the cpu's clock frequency. hence, it is not po ssible to determine the state of the presca ler - even if it were readable, and the exact time it takes to switch from one clock division to the other cannot be exactly pred icted. from the time the clkps values are written, it takes between t1 + t2 and t1 + 2 t2 before the new clock frequency is active. in this interval, 2 active clock edges are produced. here, t1 is the previous cl ock period, and t2 is the period corresponding to the new prescaler setting. to avoid unintentional c hanges of clock frequency, a spec ial write procedure must be fo llowed to chan ge the clkps bits: 1. write the clock prescaler change enable (clkpce) bit to one and all other bits in clkpr to zero. 2. within four cycles, write th e desired value to clkps while writing a zero to clkpce. interrupts must be disabled when changing prescaler setti ng to make sure the write pr ocedure is not interrupted. 9.12 register description 9.12.1 osccal ? oscillator calibration register ? bits 7:0 ? cal7:0: oscillator calibration value the oscillator calibration register is used to trim the calibrated internal rc oscillat or to remove process variations from the oscillator frequency. a pre-programmed calibr ation value is automatically written to th is register during chip reset, giving th e factory calibrated frequency as specified in table 28-3 on page 290 . the application software can write this register to change the oscillator frequency. t he oscillator can be calibrated to frequencies as specified in table 28-3 on page 290 . calibration outside that range is not guaranteed. note that this oscillator is used to time eeprom and flash writ e accesses, and these write times will be affected accordingly. if the eeprom or flash are written, do not calibrate to more than 8.8mhz. otherwise, the eeprom or flash write may fail. the cal7 bit determines the range of operat ion for the oscillator. setting this bit to 0 gives the lowest frequency range, setting this bit to 1 gives the highest frequency range. the two frequency ranges are overlapping, in other words a setting of osccal = 0x7f gives a higher frequency than osccal = 0x80. the cal6..0 bits are used to tune the frequency within the selected range. a setting of 0x00 gives the lowest frequency in that range, and a setting of 0x7f gives the highest frequency in the range. 9.12.2 clkpr ? clock prescale register ? bit 7 ? clkpce: clock prescaler change enable the clkpce bit must be written to logic one to enable cha nge of the clkps bits. the clkpce bit is only updated when the other bits in clkpr are simultaneously written to zero. clkpce is cleared by hardware four cycles after it is written or when clkps bits are written. re writing the clkpce bit with in this time-out period does neither extend th e time-out period, nor clear the clkpce bit. ? bits 3:0 ? clkps3:0: clock prescaler select bits 3 - 0 these bits define the division factor between the selected cl ock source and the internal system clock. these bits can be written run-time to vary the clock frequency to suit the applic ation requirements. as the divide r divides the master clock inpu t to the mcu, the speed of all synchronous peripherals is reduc ed when a division factor is used. the division factors are given in table 9-16 on page 33 . bit 76543210 (0x66) cal7 cal6 cal5 cal4 cal3 cal2 cal1 cal0 osccal read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value device specific calibration value bit 76543210 (0x61) clkpce ? ? ? clkps3 clkps2 clkps1 clkps0 clkpr read/write r/w r r r r/w r/w r/w r/w initial value 0 0 0 0 see bit description 33 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 the ckdiv8 fuse determines the initial value of the clkps bits. if ckdiv8 is unprogrammed, the clkps bits will be reset to ?0000?. if ckdiv8 is programmed, clkps bits are reset to ?0011?, giving a division factor of 8 at start up. this feature should be used if the selected clock source has a higher frequen cy than the maximum frequency of the device at the present operating conditions. note that any value can be written to the clkps bits r egardless of the ckdiv8 fuse setting. the application software must ensure that a sufficient division fa ctor is chosen if the select ed clock source has a higher frequency than the maximum frequency of the device at the present operating conditions. the device is shipped with the ckdiv8 fuse programmed. table 9-16. clock prescaler select clkps3 clkps2 clkps1 clkps0 clock division factor 0 0 0 0 1 0 0 0 1 2 0 0 1 0 4 0 0 1 1 8 0 1 0 0 16 0 1 0 1 32 0 1 1 0 64 0 1 1 1 128 1 0 0 0 256 1 0 0 1 reserved 1 0 1 0 reserved 1 0 1 1 reserved 1 1 0 0 reserved 1 1 0 1 reserved 1 1 1 0 reserved 1 1 1 1 reserved atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 34 10. power management and sleep modes 10.1 overview sleep modes enable the application to shut down unused module s in the mcu, thereby saving power. the avr provides various sleep modes allowing the user to tailor the power consumption to the application?s requirements. when enabled, the brown-out detector (bod) actively monitors the power supply voltage during the sleep periods. to further save power, it is possible to disable the bod in some sleep modes. see section 10.3 ?bod disable? on page 35 for more details. 10.2 sleep modes figure 9-1 on page 23 presents the different clock systems in the at mega164p-b/324p-b/644p-b, and their distribution. the figure is helpful in selecting an appropriate sleep mode. table 10-1 shows the different sleep modes, their wake up sources and bod disable ability. notes: 1. only recommended with external crystal or resonator selected as clock source. 2. if timer/counter2 is running in asynchronous mode. to enter any of the sl eep modes, the se bit in smcr must be written to logic one and a sleep instru ction must be executed. the sm2, sm1, and sm0 bits in the smcr regi ster select which sleep mode will be activated by the sleep instruction. see table 10-2 on page 38 for a summary. if an enabled interru pt occurs while the mcu is in a sleep mode, the mcu wakes up. the mc u is then halted for four cycles in addition to the start-up time, executes the interrupt routine, and resumes execut ion from the instruction following sleep. the contents of the register file and sr am are unaltered when the device wakes up from sleep. if a reset occurs during sleep mode, the mcu wakes up and executes from the reset vector. table 10-1. active clock domains and wake-up sources in the different sleep modes. active clock domains oscillators wake-up sources software bod disdable sleep mode clk cpu clk flash clk io clk adc clk asy main clock source enabled timer osc enabled int2:0 and pin change twi address match timer2 spm/ eeprom ready adc wdt interrupt other i/o idle x x x x x (2) x x x x x x x adcnrm x x x x (2) x x x (2) x x x power-down x x x x power-save x x (2) x x x x x standby (1) x x x x x extended standby x (2) x x (2) x x x x x 35 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 10.3 bod disable when the brown-out detector (bod ) is enabled by bodlevel fuses, table 27-3 on page 256 , the bod is actively monitoring the power supply voltage during a sleep period. to save power, it is possible to disable the bod by software for some of the sleep modes, see table 10-1 on page 34 . the sleep mode power consumption will then be at the same level as when bod is globally disabled by fuses. if bod is disabled in software, the bo d function is turned off immediately after entering the sleep mode. upon wake-up from sleep, bod is auto matically enabled again. this ensures safe operation in case the v cc level has dropped during the sleep period. when the bod has been disabled, the wake-up time from sleep mode will be approximately 60s to ensure that the bod is working correctly before the mcu continues executing code. bod disable is controlled by bit 6, bods (bod sleep) in the control register mcucr, see section 10.12.2 ?mcucr ? mcu control register? on page 38 . writing this bit to one turns off the bod in rele vant sleep modes, while a zero in this bit keeps bod active. default setting keeps bo d active, i.e. bods set to zero. writing to the bods bit is controlled by a timed sequence and an enable bit, see section 10.12.2 ?mcucr ? mcu control register? on page 38 . 10.4 idle mode when the sm2..0 bits are written to 000, the sleep instruction makes the mcu enter idle mode, st opping the cpu but allowing the spi, usart, analog comparat or, adc, 2-wire serial interface, time r/counters, watchdog, and the interrupt system to continue operating. this sleep mode basically halts clk cpu and clk flash , while allowing the other clocks to run. idle mode enables the mcu to wake up from external triggered interrupts as well as internal ones like the timer overflow and usart transmit complete interrupts. if wa ke-up from the analog comparator interrupt is not required, the analog comparator can be powered down by setting the acd bit in the analog comp arator control and status regi ster ? acsr. this will reduce power consumption in idle mode. if the adc is enabled, a conversion starts automatically when this mode is entered. 10.5 adc noise reduction mode when the sm2..0 bits are writ ten to 001, the sleep instruct ion makes the mcu enter adc no ise reduction mode, stopping the cpu but allowing the adc, the external interrupts, 2-wir e serial interface address match, timer/counter2 and the watchdog to continue operating (if enabled). this sleep mode basically halts clki/o, clkcpu, and clkflash, while allowing the other clocks to run. this improves the noise environment for the adc, enabling higher resolution measurements. if the adc is enabled, a conversion starts automatically when th is mode is entered. apart form the adc conversion complete interrupt, only an external reset, a watch dog system reset, a watch dog interrupt, a brown-out reset, a 2-wire serial inte rface interrupt, a timer/counter2 interrupt, an spm/eeprom ready interrupt, an external le vel interrupt on int7:4 or a pin change interrupt can wake up the mcu from adc noise reduction mode. 10.6 power-down mode when the sm2..0 bits are written to 010, the sleep instruct ion makes the mcu enter power-down mode. in this mode, the external oscillator is stopped, while the external interrupts, th e 2-wire serial interface, and the watchdog continue operating (if enabled). only an external reset, a watchdog reset, a brown- out reset, 2-wire serial interf ace address match, an external level interrupt on pcint7:4, an external interrupt on int2:0, or a pin change interrupt can wake up the mcu. this sleep mode basically halts all generated clocks, allowing operation of asynchronous modules only. note that if a level triggered interrupt is used for wake-up from power-down mode, the changed level must be held for some time to wake up the mcu. refer to section 13. ?external interrupts? on page 53 for details. when waking up from power-down mode, there is a delay fr om the wake-up condition occurs until the wake-up becomes effective. this allows the clock to restart and become stable after having been stopped. the wake-up period is defined by the same cksel fuses that def ine the reset time-out period, as described in section 9.2 ?clock sources? on page 24 . atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 36 10.7 power-save mode when the sm2:0 bits are written to 011, the sleep instruction makes the mcu enter power-save mode. this mode is identical to power-down, with one exception: if timer/counter2 is enabled, it will keep running during sleep. the device can wake up from either timer overflow or output compare event from timer/counter2 if the corresponding time r/counter2 interrupt enable bits are set in timsk2, and the global interrupt enable bit in sreg is set. if timer/counter2 is not running, power-down mode is recommended instead of power-save mode. the timer/counter2 can be clocked both synchronously and a synchronously in power-save mode. if the timer/counter2 is not using the asynchronous clock, the time r/counter oscillator is stopped during sleep. if the timer/counter2 is not using the synchronous clock, the clock source is stopped during sle ep. note that even if the synchronous clock is running in power-save, this clock is only available for the timer/counter2. 10.8 standby mode when the sm2..0 bits are 110 and an external crystal/resonato r clock option is selected, th e sleep instruction makes the mcu enter standby mode. this mode is identical to power-down with the exception that the o scillator is kept running. from standby mode, the device wakes up in six clock cycles. 10.9 extended standby mode when the sm2..0 bits are 111 and an external crystal/resonato r clock option is selected, th e sleep instruction makes the mcu enter extended standby mode. this mode is identical to powe r-save mode with the exception that the oscillator is kept running. from extended stan dby mode, the device wakes up in six clock cycles. 10.10 power reduction register the power reduction register (prr), see section 10.12.3 ?prr0 ? power reduction register 0? on page 39 , provides a method to stop the clock to individual peripherals to reduce po wer consumption. the current st ate of the peripheral is frozen and the i/o registers can not be read or written. resources used by the peripheral when stopping the clock will remain occupied, hence the peripheral should in most cases be disabled before stopping the clock. waking up a peripheral, which is done by clearing the bit in prr, puts the peri pheral in the same state as before shutdown. peripheral shutdown can be used in idle mode and active mode to significantly reduce the overa ll power consumption. in all other sleep modes, the clock is already stopped. 10.11 minimizing power consumption there are several issues to consider when trying to minimize the power consumption in an avr controlled system. in general, sleep modes should be used as much as possible, a nd the sleep mode should be selected so that as few as possible of the device?s functions are op erating. all functions not needed should be disabled. in particular, the following modules may need special considerat ion when trying to achieve the lowest possible power consumption. 10.11.1 analog to digital converter if enabled, the adc will be enabled in all sleep modes. to save power, the adc should be disabled before entering any sleep mode. when the adc is turned off and on again, the next conversion will be an extended conversion. refer to section 23. ?adc - analog-to-digital converter? on page 207 for details on adc operation. 10.11.2 analog comparator when entering idle mode, the analog com parator should be disabled if not used. when entering adc noise reduction mode, the analog comparator should be disabled. in other sleep modes, the analog comp arator is automatically disabled. however, if the analog comparator is set up to us e the internal voltage reference as input, the analog comparator should be disabled in all sleep modes. otherwise, the internal voltage refe rence will be enabled, independent of sleep mode. refer to section 22. ?ac - analog comparator? on page 204 for details on how to configure the analog comparator. 37 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 10.11.3 brown-out detector if the brown-out detector is not needed by the application, this module should be tur ned off. if the brown-out detector is enabled by the bodlevel fuses, it will be enabled in all sleep modes, and hence, always consume power. in the deeper sleep modes, this will contribute significantly to the total current consumption. refer to section 11.1.4 ?brown-out detection? on page 42 for details on how to configure the brown-out detector. 10.11.4 internal voltage reference the internal voltage reference will be enabled when needed by the brown-out detection, the ana log comparator or the adc. if these modules are disabled as described in the sections above, the internal volt age reference will be disabled and it will not be consuming power. when turned on again, the user must allow the reference to start up before the output is used. if the reference is kept on in sleep mode, the output can be used immediately. refer to section 11.2 ?internal voltage reference? on page 43 for details on the start-up time. 10.11.5 watchdog timer if the watchdog timer is not needed in t he application, the module should be turned off. if the watchdog timer is enabled, it will be enabled in all sleep modes, and hence, always consume power. in the deeper sleep modes, this will contribute significantly to the total cu rrent consumption. refer to section 11.3 ?watchdog timer? on page 44 for details on how to configure the watchdog timer. 10.11.6 port pins when entering a sleep mode, all port pins should be configured to use minimum power. the most important is then to ensure that no pins drive resistive loads. in sleep modes where both the i/o clock (clk i/o ) and the adc clock (clk adc ) are stopped, the input buffers of the device will be disabl ed. this ensures that no power is consum ed by the input logic when not needed. in some cases, the input logic is needed for detecting wake-u p conditions, and it will then be enabled. refer to the section section 14.2.5 ?digital input enable and sleep modes? on page 61 for details on which pins are enabled. if the input buffer is enabled and the input signal is left floating or have an analog signal level close to v cc /2, the input buffer will use excessive power. for analog input pins, the digital input buffer should be disabled at all times. an analog signal level close to v cc /2 on an input pin can cause significant current even in active mode. digital input buffers can be disabled by writing to the digital input disable registers (didr1 and didr0). refer to section 22.3.3 ?didr1 ? digital inpu t disable register 1? on page 206 and section 23.9.5 ?didr0 ? digital input disable register 0? on page 224 for details. 10.11.7 on-chip debug system if the on-chip debug system is enabled by the ocden fuse and the chip enters sleep mode, the main clock source is enabled, and hence, always consumes power. in the deeper sleep m odes, this will contribute significantly to the total current consumption. there are three alternative wa ys to disable the ocd system: disable the ocden fuse disable the jtagen fuse write one to the jtd bit in mcucr atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 38 10.12 register description 10.12.1 smcr ? sleep mode control register the sleep mode control register contai ns control bits for power management. ? bits 3, 2, 1 ? sm2:0: sleep mode select bits 2, 1, and 0 these bits select between the five available sleep modes as shown in table 10-2 . note: 1. standby modes are only recommended for use with external crystals or resonators. ? bit 0 ? se: sleep enable the se bit must be written to logic one to make the mcu enter the sleep mode when the sleep instruction is executed. to avoid the mcu entering the sleep mode unless it is the progra mmer?s purpose, it is recomm ended to write the sleep enable (se) bit to one just before the executio n of the sleep instruction and to cl ear it immediatel y after waking up. 10.12.2 mcucr ? mcu control register ? bit 6 ? bods: bod sleep the bods bit must be written to logic one in order to turn off bod during sleep, see table 10-1 on page 34 . writing to the bods bit is controlled by a timed sequence and an enable bit, bodse in mcucr. to disable bod in relevant sleep modes, both bods and bodse must first be set to one. then, to set the bods bit, bods must be set to one and bodse must be set to zero within four clock cycles. the bods bit is active three clock cycles after it is set. a sleep instruction must be executed wh ile bods is active in order t o turn off the bod for the actual sleep mode. the bods bit is automatically cleared after three clock cycles. ? bit 5 ? bodse: bod sleep enable bodse enables setting of bods control bit, as explained in bods bit description. bod disable is controlled by a timed sequence. bit 76543210 0x33 (0x53) ? ? ? ? sm2 sm1 sm0 se smcr read/write rrrrr/wr/wr/wr/w initial value00000000 table 10-2. sleep mode select sm2 sm1 sm0 sleep mode 0 0 0 idle 0 0 1 adc noise reduction 0 1 0 power-down 0 1 1 power-save 1 0 0 reserved 1 0 1 reserved 1 1 0 standby (1) 1 1 1 extended standby (1) bit 7 6 5 4 3 2 1 0 0x35 (0x55) jtd bods bodse pud ? ? ivsel ivce mcucr read/write r/w r/w r/w r/w r r r/w r/w initial value 0 0 0 0 0 0 0 0 39 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 10.12.3 prr0 ? power reduction register 0 ? bit 7 ? prtwi: power reduction twi writing a logic one to this bit shuts down the twi by stopping the clock to the module. when waking up the twi again, the twi should be re initialized to ensure proper operation. ? bit 6 ? prtim2: power reduction timer/counter2 writing a logic one to this bit shuts down the timer/co unter2 module in synchronous mode (as2 is 0). when the timer/counter2 is enabled, operation will continue like before the shutdown. ? bit 5 ? prtim0: power reduction timer/counter0 writing a logic one to this bit shuts do wn the timer/counter0 module . when the timer/counter0 is enabled, operation will continue like before the shutdown. ? bit 4 ? prusart1: power reduction usart1 writing a logic one to this bit shuts down the usart1 by st opping the clock to the module. when waking up the usart1 again, the usart1 should be reinitialized to ensure proper operation. ? bit 3 ? prtim1: power reduction timer/counter1 writing a logic one to this bit shuts do wn the timer/counter1 module . when the timer/counter1 is enabled, operation will continue like before the shutdown. ? bit 2 ? prspi: power reducti on serial peripheral interface writing a logic one to this bit shuts down the serial peripheral interface by stopping the clock to the module. when waking up the spi again, the spi should be re initialized to ensure proper operation. ? bit 1 ? prusart0: power reduction usart0 writing a logic one to this bit shuts down the usart0 by st opping the clock to the module. when waking up the usart0 again, the usart0 should be reinitialized to ensure proper operation. ? bit 0 ? pradc: power reduction adc writing a logic one to this bit shuts down the adc. the a dc must be disabled before shut down. the analog comparator cannot use the adc input mux when the adc is shut down. 10.12.4 prr1 ? power reduction register 1 ? bit 7:1 ? reserved ? bit 0 ? prtim3: power reduction timer/counter3 writing a logic one to this bit shuts do wn the timer/counter3 module . when the timer/counter3 is enabled, operation will continue like before the shutdown. bit76543210 (0x64) prtwi prtim2 prtim0 prusart1 prtim1 prspi prusart0 pradc prr0 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 (0x65) ? ? ? ? ? ? ?prtim3prr1 read/writerrrrrrrr/w initial value00000000 atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 40 11. system control and reset 11.1 resetting the avr during reset, all i/o registers are set to their initial values, and the program starts execution from the reset vector. the instruction placed at the reset vector mu st be a jmp ? absolute jump ? instruction to the reset handling routine. if the program never enables an interrupt source, the interrupt vector s are not used, and regular progr am code can be placed at these locations. this is also the case if the reset vector is in the application section while the interrupt vectors are in the boot section or vice versa. the circuit diagram in figure 11-1 on page 41 shows the reset logic. section 28.5 ?system and reset characteristics? on page 291 defines the electrical parameters of the reset circuitry. the i/o ports of the avr are immediately reset to their initial state when a reset source goes active. this does not require any clock source to be running. after all reset sources have gone inactive, a delay counter is invo ked, stretching the internal reset. this allows the power to reach a stable level before normal operation starts. the time- out period of the delay counter is defined by the user through the sut and cksel fuses. the different se lections for t he delay period are presented in section 9.2 ?clock sources? on page 24 . 11.1.1 reset sources the atmega164p-b/324p-b/644p-b has five sources of reset: power-on reset: the mcu is reset when the supply voltage is below the power-on reset threshold (v pot ). external reset: the mcu is reset wh en a low level is present on the reset pin for longer than the minimum pulse length. watchdog reset: the mcu is reset when the watc hdog timer period expires and the watchdog is enabled. brown-out reset: the mcu is reset when the supply voltage v cc is below the brown-out reset threshold (v bot ) and the brown-out detector is enabled. jtag avr reset: the mcu is reset as long as there is a logic one in the reset register, one of the scan chains of the jtag system. refer to section 25. ?ieee 1149.1 (jtag) boundary-scan? on page 231 for details. 41 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 figure 11-1. reset logic 11.1.2 power-on reset a power-on reset (por) pulse is generated by an on-chip detection circuit. the detection level is defined in section 28.5 ?system and reset characteristics? on page 291 . the por is activated whenever v cc is below the detection level. the por circuit can be used to trigger the start-up reset, as well as to detect a failure in supply voltage. a power-on reset (por) circuit ensures that the device is reset from power-on. reaching the power-on reset threshold voltage invokes the delay counter, which determine s how long the device is kept in reset after v cc rise. the reset signal is activated again, without any delay, when v cc decreases below the detection level. figure 11-2. mcu start-up, reset tied to v cc power-on reset circuit brown-out reset circuit mcu status register (mcusr) reset circuit pull-up resistor bodlevel [2 to 0] s q r data bus ck sut[1:0] cksel[3:0] counter reset internal reset timeout spike filter reset vcc delay counters watchdog timer jtag reset register watchdog oscillator clock generator porf borf wdrf jtrf extrf v pot v rst v cc reset internal reset time-out t tout atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 42 figure 11-3. mcu start-up, reset extended externally 11.1.3 external reset an external reset is generated by a low level on the reset pin. reset pulses longer t han the minimum pulse width (see ?system and reset characteristics? on page 291 ) will generate a reset, even if the cl ock is not running. shorter pulses are not guaranteed to generate a reset. when the applied signal reaches the reset threshold voltage ? v rst ? on its positive edge, the delay counter starts the mcu after the time-out period ? t tout ? has expired. figure 11-4. external reset during operation 11.1.4 brown-out detection atmega164p-b/324p-b/644p-b has an on-chip brown-ou t detection (bod) circuit for monitoring the v cc level during operation by comparing it to a fixed trigger level. the trigger level for the bod can be selected by the bodlevel fuses. the trigger level has a hysteresis to ensure spike free brown-out detection. the hysteresis on the detection level should be interpreted as v bot+ = v bot + v hyst /2 and v bot- = v bot ? v hyst /2. when the bod is enabled, and v cc decreases to a value below the trigger level (v bot- in figure 11-5 on page 43 ), the brown-out reset is immedi ately activated. when v cc increases above the trigger level (v bot+ in figure 11-5 on page 43 ), the delay counter starts the mcu after the time-out period t tout has expired. the bod circuit will only detect a drop in v cc if the voltage stays below the trigger level for longer than t bod given in section 28.5 ?system and reset characteristics? on page 291 . v dd reset internal reset time-out v pot v rst t tout t tout reset v cc internal reset time-out v rst 43 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 figure 11-5. brown-out reset during operation 11.1.5 watchdog reset when the watchdog times out, it will generate a short reset pulse of one ck cycle duration. on the falling edge of this pulse, the delay timer starts counting the time-out period t tout . refer to section 11.3 ?watchdog timer? on page 44 for details on operation of the watchdog timer. figure 11-6. watchdog reset during operation 11.2 internal voltage reference atmega164p-b/324p-b/644p-b featur es an internal bandgap reference. this refere nce is used for brown-out detection, and it can be used as an input to t he analog comparator or the adc. 11.2.1 voltage reference enable signals and start-up time the voltage reference has a start-up time that may influence the way it should be used. the start-up time is given in section 28.5 ?system and reset characteristics? on page 291 . to save power, the reference is not always turned on. the reference is on during the following situations: 1. when the bod is enabled (by programming the bodlevel [2:0] fuse). 2. when the bandgap reference is connected to the anal og comparator (by setting the acbg bit in acsr). 3. when the adc is enabled. thus, when the bod is not enabled, af ter setting the acbg bit or enabling the adc, the user must always allow the reference to start up before the output from the analog comparator or adc is used. to reduce power consumption in power-down mode, the user can avoid the three conditions above to ensure that the reference is turned off before entering power-down mode. v bot- v bot+ t tout v cc reset internal reset time-out 1 ck cycle v cc reset internal reset reset time-out wdt time-out t tout atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 44 11.3 watchdog timer 11.3.1 features clocked from separate on-chip oscillator 3 operating modes interrupt system reset interrupt and system reset selectable time-out period from 16ms to 8s possible hardware fuse watchdog always on (wdton) for fail-safe mode 11.3.2 overview atmega164p-b/324p-b/644p-b has an enhanced watchdog timer (w dt). the wdt is a timer counting cycles of a separate on-chip 128khz oscillator. the wdt gives an interrupt or a system reset when the counter reaches a given time-out value. in normal operation mode, it is required th at the system uses the wdr - watchdog timer re set - instruction to restart the counter before the time-out value is reac hed. if the system doesn't restart the count er, an interrupt or system reset will be issued. figure 11-7. watchdog timer in interrupt mode, the wdt gives an interrupt when the timer ex pires. this interrupt can be used to wake the device from sleep-modes, and also as a general system timer. one exampl e is to limit the maximum time allowed for certain operations, giving an interrupt when the operation has run longer than ex pected. in system reset mode, the wdt gives a reset when the timer expires. this is typi cally used to prevent system hang-up in case of runaway code. the th ird mode, interrupt and system reset mode, combines the other two modes by first gi ving an interrupt and then switch to system reset mode. this mode will for instance allow a safe shutdown by savi ng critical parameters before a system reset. the watchdog always on (w dton) fuse, if programmed, will force the watch dog timer to system rese t mode. with the fuse programmed the system reset mode bit (wde) and interrupt mode bit (wdie) are locke d to 1 and 0 respectively. to further ensure program security, alterations to the watchdog set-up must follow timed sequences. the sequence for clearing wde and changing time-out configuration is as follows: 1. in the same operation, write a logic one to the wa tchdog change enable bit (wdce) and wde. a logic one must be written to wde regardless of t he previous value of the wde bit. 2. within the next four clock cycles, write the wde and watchdog prescaler bits (wdp) as desired, but with the wdce bit cleared. this must be done in one operation. osc/64k osc/16k osc/2k osc/4k osc/8k osc/32k osc/128k osc/256k osc/512k osc/1024k watchdog prescaler wdp0 wde watchdog reset wdif wdie wdp1 wdp2 wdp3 mcu reset interrupt 128khz oscillator 45 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 the following code example shows one assembly and one c function for turning off the watchdog timer. the example assumes that interrupts are controlled (e.g. by disabling in terrupts globally) so that no interrupts will occur during the execution of these functions. notes: 1. the example code assumes that t he part specific header file is included. 2. if the watchdog is accidentally enabled, for example by a runaway pointer or brow n-out condition, the device will be reset and the watchdog timer will stay enabled. if the code is not set up to handle the watchdog, this might lead to an eternal loop of time-out resets. to av oid this situation, the application software should always clear the watchdog system reset flag (wdrf) and the wde control bit in the initializ ation routine, even if the watchdog is not in use. assembly code example (1) wdt_off: ; turn off global interrupt cli ; reset watchdog timer wdr ; clear wdrf in mcusr in r16, mcusr andi r16, ~(1< atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 48 ? bit 4 - wdce: watchdog change enable this bit is used in timed sequences for changing wde and pre scaler bits. to clear the wde bit, and/or change the prescaler bits, wdce must be set. once written to one, hardware will cl ear wdce after four clock cycles. ? bit 3 - wde: watchdog system reset enable wde is overridden by wdrf in mcusr. this means that wde is always set when wdrf is set. to clear wde, wdrf must be cleared first. this feature ensu res multiple resets during conditions caus ing failure, and a safe start-up after the failure. ? bit 5, 2:0 - wdp3:0: watchdog timer prescaler 3, 2, 1 and 0 the wdp3:0 bits determine the watchdog timer prescaling when the watchdog timer is running. the different prescaling values and their corresponding time-out periods are shown in table 11-2 on page 48 . table 11-1. watchdog timer configuration wdton wde wdie mode action on time-out 1 0 0 stopped none 1 0 1 interrupt mode interrupt 1 1 0 system reset mode reset 1 1 1 interrupt and system reset mode interrupt, then go to system reset mode 0 x x system reset mode reset table 11-2. watchdog timer prescale select wdp3 wdp2 wdp1 wdp0 number of wdt oscillator cycles typical time-out at v cc = 5.0v 0 0 0 0 2k (2048) cycles 16ms 0 0 0 1 4k (4096) cycles 32ms 0 0 1 0 8k (8192) cycles 64ms 0 0 1 1 16k (16384) cycles 0.125s 0 1 0 0 32k (32768) cycles 0.25s 0 1 0 1 64k (65536) cycles 0.5s 0 1 1 0 128k (131072) cycles 1.0s 0 1 1 1 256k (262144) cycles 2.0s 1 0 0 0 512k (524288) cycles 4.0s 1 0 0 1 1024k (1048576) cycles 8.0s 1 0 1 0 reserved 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 49 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 12. interrupts 12.1 overview this section describes the specifics of the interrupt handl ing as performed in atmega164p-b /324p-b/644p-b. for a general explanation of the avr interrupt handling, refer to section 7.7 ?reset and interrupt handling? on page 14 . 12.2 interrupt vectors in atmega164p-b/324p-b/644p-b table 12-1. reset and interrupt vectors vector no. program address (2) source interrupt definition 1 $0000 (1) reset external pin, power-on reset, brown-out reset, watchdog reset, and jtag avr reset 2 $0002 int0 external interrupt request 0 3 $0004 int1 external interrupt request 1 4 $0006 int2 external interrupt request 2 5 $0008 pcint0 pin change interrupt request 0 6 $000a pcint1 pin change interrupt request 1 7 $000c pcint2 pin change interrupt request 2 8 $000e pcint3 pin change interrupt request 3 9 $0010 wdt watchdog time-out interrupt 10 $0012 timer2_compa timer/counter2 compare match a 11 $0014 timer2_compb timer/counter2 compare match b 12 $0016 timer2_ovf timer/counter2 overflow 13 $0018 timer1_capt timer/counter1 capture event 14 $001a timer1_compa timer/counter1 compare match a 15 $001c timer1_compb timer/counter1 compare match b 16 $001e timer1_ovf timer/counter1 overflow 17 $0020 timer0_compa timer/counter0 compare match a 18 $0022 timer0_compb timer/counter0 compare match b 19 $0024 timer0_ovf timer/counter0 overflow 20 $0026 spi_stc spi serial transfer complete 21 $0028 usart0_rx usart0 rx complete 22 $002a usart0_udre usart0 data register empty 23 $002c usart0_tx usart0 tx complete 24 $002e analog_comp analog comparator 25 $0030 adc adc conversion complete 26 $0032 ee_ready eeprom ready 27 $0034 twi 2-wire serial interface 28 $0036 spm_ready store program memory ready 29 $0038 usart1_rx usart1 rx complete 30 $003a usart1_udre usart1 data register empty 31 $003c usart1_tx usart1 tx complete notes: 1. when the bootrst fuse is programmed, the device will jump to the boot loader address at reset, see section 27. ?memory programming? on page 255 . 2. when the ivsel bit in mcucr is set, interrupt vectors will be moved to the start of the boot flash section. the address of each interrupt vector will then be the addre ss in this table added to the start address of the boot flash section. atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 50 table 12-2 shows reset and interrupt vectors placement for the vari ous combinations of bootrst and ivsel settings. if the program never enables an interrupt s ource, the interrupt vectors are not used, and regular program code can be placed at these locations. this is al so the case if the reset vector is in the applic ation section while the interrupt vectors are in the boot section or vice versa. the most typical and general program setup for the reset an d interrupt vector addresses in atmega164p-b/324p-b/644p-b is: address labels code comments 0x0000 jmp reset ; reset 0x0002 jmp int0 ; irq0 0x0004 jmp int1 ; irq1 0x0006 jmp int2 ; irq2 0x0008 jmp pcint0 ; pcint0 0x000a jmp pcint1 ; pcint1 0x000c jmp pcint2 ; pcint2 0x000e jmp pcint3 ; pcint3 0x0010 jmp wdt ; watchdog timeout 0x0012 jmp tim2_compa ; timer2 comparea 0x0014 jmp tim2_compb ; timer2 compareb 0x0016 jmp tim2_ovf ; timer2 overflow 0x0018 jmp tim1_capt ; timer1 capture 0x001a jmp tim1_compa ; timer1 comparea 0x001c jmp tim1_compb ; timer1 compareb 0x001e jmp tim1_ovf ; timer1 overflow 0x0020 jmp tim0_compa ; timer0 comparea 0x0022 jmp tim0_compb ; timer0 compareb 0x0024 jmp tim0_ovf ; timer0 overflow 0x0026 jmp spi_stc ; spi transfer complete 0x0028 jmp usart0_rxc ; usart0 rx complete 0x002a jmp usart0_udre ; usart0,udr empty 0x002c jmp usart0_txc ; usart0 tx complete 0x002e jmp ana_comp ; analog comparator 0x0030 jmp adc ; adc conversion complete 0x0032 jmp ee_rdy ; eeprom ready 0x0034 jmp twi ; 2-wire serial 0x0036 jmp spm_rdy ; spm ready 0x0038 jmp usart1_rxc ; usart1 rx complete 0x003a jmp usart1_udre ; usart1,udr empty 0x003c jmp usart1_txc ; usart1 tx complete ; 0x003e reset: ldi r16,high(ramend); main program start 0x003f out sph,r16 ; set stack pointer to top of ram 0x0040 ldi r16,low(ramend) 0x0041 out spl,r16 0x0042 sei ; enable interrupts 0x0043 51 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 when the bootrst fuse is unprogrammed, the boot section size set to 8kbytes and the ivsel bit in the mcucr register is set before any interrupts are enabled, the most typical and general program setup for the reset and interrupt vector addresses is: address labels code comments 0x00000 reset: ldi r16,high(ramend); main program start 0x00001 out sph,r16 ; set stack pointer to top of ram 0x00002 ldi r16,low(ramend) 0x00003 out spl,r16 0x00004 sei ; enable interrupts 0x00005 atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 52 12.3 register description 12.3.1 mcucr ? mcu control register . ? bit 1 ? ivsel: interrupt vector select when the ivsel bit is cleared (zero), the interrupt vectors are placed at the start of the flash memory. when this bit is set (one), the interrupt vectors are moved to t he beginning of the boot loader section of t he flash. the actual address of the star t of the boot flash section is determined by the bootsz fuses. refer to the section 27. ?memory programming? on page 255 for details. to avoid unintentional changes of interrupt vector tables, a special write procedure must be followed to change the ivsel bit: 1. write the interrupt vector change enable (ivce) bit to one. 2. within four cycles, write th e desired value to ivsel whil e writing a zero to ivce. interrupts will automat ically be disabled while this sequence is executed. interrupts ar e disabled in the cycle ivce is set, an d they remain disabled until after the instru ction following th e write to ivsel. if ivsel is not written, interrupts remain disab led for four cycles. the i-bit in th e status register is unaffect ed by the automatic disabling. note: if interrupt vectors are placed in the boot loader se ction and boot lock bit blb02 is programmed, interrupts are disabled while executing from the application section. if interrupt vectors are placed in the application section and boot lock bit blb12 is programed, interrupts are disa bled while executing from the boot loader section. refer to the section section 27. ?memory programming? on page 255 for details on boot lock bits. ? bit 0 ? ivce: interrupt vector change enable the ivce bit must be written to logic one to enable change of t he ivsel bit. ivce is cleared by hardware four cycles after it is written or when ivsel is written. setting the ivce bit will disable interrupts, as explained in the ivsel description above. see the following code example. bit 76 5 43210 0x35 (0x55) jtd bods bodse pud ? ? ivsel ivce mcucr read/write r/w r/w r/w r/w r r r/w r/w initial value 0 0 0 0 0 0 0 0 assembly code example move_interrupts: ; get mcucr in r16, mcucr mov r17, r16 ; enable change of interrupt vectors ori r16, (1< atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 54 13.2.2 eimsk ? external interrupt mask register ? bits 2:0 ? int2:0: external interrupt request 2 - 0 enable when an int2:0 bit is written to one and the i-bit in the status register (sreg) is set (one), the corresponding external pin interrupt is enabled. the interrupt sense control bits in the ex ternal interrupt control register, eicra, defines whether the external interrupt is activated on rising or falling edge or leve l sensed. activity on any of these pins will trigger an interr upt request even if the pin is enabled as an output. this provides a way of generat ing a software interrupt. 13.2.3 eifr ?external in terrupt flag register ? bits 2:0 ? intf2:0: external interrupt flags 2 - 0 when an edge or logic change on the int2:0 pin triggers an in terrupt request, intf2:0 becomes set (one). if the i-bit in sreg and the corresponding interrupt enable bit, int2:0 in eimsk, are set (one), the mcu will ju mp to the interrupt vector. the flag is cleared when the interrupt routine is executed. alte rnatively, the flag can be cleared by writing a logical one to it. these flags are always cleared when int2:0 are configured as le vel interrupt. note that when entering sleep mode with the int2:0 interrupts disabled, the input buffer s on these pins will be disabled. this may cause a logic change in internal signals which will set the intf2:0 flags. see section 14.2.5 ?digital input enable and sleep modes? on page 61 for more information. 13.2.4 pcicr ? pin change interrupt control register ? bit 3 ? pcie3: pin change interrupt enable 3 when the pcie3 bit is set (one) and the i-bit in the status regi ster (sreg) is set (one), pin change interrupt 3 is enabled. an y change on any enabled pcint31:24 pin will cause an interrupt. the corresponding interrupt of pin change interrupt request is executed from the pci3 interrupt vector. pcint31:24 pins are enabled individually by the pcmsk3 register. table 13-1. interrupt sense control (1) iscn1 iscn0 description 0 0 the low level of intn generates an interrupt request. 0 1 any edge of intn generates asynchronously an interrupt request. 1 0 the falling edge of intn generates asynchronously an interrupt request. 1 1 the rising edge of intn generates asynchronously an interrupt request. note: 1. n = 2, 1 or 0. when changing the iscn1/iscn0 bits, the interrupt must be disabled by clearing its interrupt enable bit in the eimsk register. otherwise an interrupt can occur when the bits are changed. bit 76543210 0x1d (0x3d) ? ? ? ? ? int2 int1 iint0 eimsk read/write rrrrrr/wr/wr/w initial value00000000 bit 76543210 0x1c (0x3c) ? ? ? ? ? intf2 intf1 iintf0 eifr read/write r/w rrrrr/wr/wr/w initial value00000000 bit 76543210 (0x68) ? ? ? ? pcie3 pcie2 pcie1 pcie0 pcicr read/write r r r r r/w r/w r/w r/w initial value00000000 55 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 ? bit 2 ? pcie2: pin change interrupt enable 2 when the pcie2 bit is set (one) and the i-bit in the status regi ster (sreg) is set (one), pin change interrupt 2 is enabled. an y change on any enabled pcint23:16 pin will cause an interrupt. the corresponding interrupt of pin change interrupt request is executed from the pci2 interrupt vector. pcint23:16 pins are enabled individually by the pcmsk2 register. ? bit 1 ? pcie1: pin change interrupt enable 1 when the pcie1 bit is set (one) and the i-bit in the status regi ster (sreg) is set (one), pin change interrupt 1 is enabled. an y change on any enabled pcint15:8 pin will cause an interrupt. the corresponding interrupt of pin change interrupt request is executed from the pci1 interrupt vector. pcint15:8 pi ns are enabled individually by the pcmsk1 register. ? bit 0 ? pcie0: pin change interrupt enable 0 when the pcie0 bit is set (one) and the i-bit in the status regi ster (sreg) is set (one), pin change interrupt 0 is enabled. an y change on any enabled pcint7:.0 pin will cause an interrupt. t he corresponding interrupt of pin change interrupt request is executed from the pci0 interrupt vector. pcint7:0 pi ns are enabled individually by the pcmsk0 register. 13.2.5 pcifr ? pin change interrupt flag register ? bit 3? pcif3: pin change interrupt flag 3 when a logic change on any pcint31:24 pin triggers an interrup t request, pcif3 becomes set (one). if the i-bit in sreg and the pcie3 bit in pcicr are set (one), the mcu will jump to the corresponding interrupt vector. the flag is cleared when the interrupt routine is executed. alternatively, the flag can be cleared by writing a logical one to it. ? bit 2 ? pcif2: pin change interrupt flag 2 when a logic change on any pcint23:16 pin triggers an interrup t request, pcif2 becomes set (one). if the i-bit in sreg and the pcie2 bit in pcicr are set (one), the mcu will jump to the corresponding interrupt vector. the flag is cleared when the interrupt routine is executed. alternatively, the flag can be cleared by writing a logical one to it. ? bit 1 ? pcif1: pin change interrupt flag 1 when a logic change on any pcint15:8 pin triggers an interrupt re quest, pcif1 becomes set (one) . if the i-bit in sreg and the pcie1 bit in pcicr are set (one), the mcu will jump to t he corresponding interrupt vector. the flag is cleared when the interrupt routine is executed. alternatively, the fl ag can be cleared by writing a logical one to it. ? bit 0 ? pcif0: pin change interrupt flag 0 when a logic change on any pcint7:0 pin triggers an interr upt request, pcif0 becomes set (one). if the i-bit in sreg and the pcie0 bit in pcicr are set (one), the mcu will jump to t he corresponding interrupt vector. the flag is cleared when the interrupt routine is executed. alternatively, the fl ag can be cleared by writing a logical one to it. 13.2.6 pcmsk3 ? pin change mask register 3 ? bit 7:0 ? pcint31:24: pin change enable mask 31:24 each pcint31:24-bit selects whether pin ch ange interrupt is enabled on the corresponding i/o pin. if pcint31:24 is set and the pcie3 bit in pcicr is set, pin change interrupt is enabl ed on the corresponding i/o pin. if pcint31:24 is cleared, pin change interrupt on the corresponding i/o pin is disabled. bit 76543210 0x1b (0x3b) ? ? pcif3 pcif2 pcif1 pcif0 pcifr read/write r r r r r/w r/w r/w r/w initial value00000000 bit 76543210 (0x73) pcint31 pcint30 pcint29 pcint28 pcint27 pcint26 pcint25 pcint24 pcmsk3 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 56 13.2.7 pcmsk2 ? pin change mask register 2 ? bit 7:0 ? pcint23:16: pin change enable mask 23..16 each pcint23:16-bit selects whether pin ch ange interrupt is enabled on the corresponding i/o pin. if pcint23:16 is set and the pcie2 bit in pcicr is set, pin change interrupt is enabl ed on the corresponding i/o pin. if pcint23:16 is cleared, pin change interrupt on the corresponding i/o pin is disabled. 13.2.8 pcmsk1 ? pin change mask register 1 ? bit 7:0 ? pcint15:8: pin change enable mask 15..8 each pcint15:8-bit selects whether pin change interrupt is en abled on the corresponding i/o pin. if pcint15:8 is set and the pcie1 bit in eimsk is set, pin change interrupt is enabl ed on the corresponding i/o pin. if pcint15:8 is cleared, pin change interrupt on the corresponding i/o pin is disabled. 13.2.9 pcmsk0 ? pin change mask register 0 ? bit 7:0 ? pcint7:0: pin change enable mask 7..0 each pcint7:0 bit selects whether pin change interrupt is e nabled on the corresponding i/o pin. if pcint7:0 is set and the pcie0 bit in pcicr is set, pin change interrupt is enabled on the corresponding i/o pin. if pcint7..0 is cleared, pin change interrupt on the corresponding i/o pin is disabled. bit 76543210 (0x6d) pcint23 pcint22 pcint21 pcint20 pcint19 pcint18 pcint17 pcint16 pcmsk2 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 (0x6c) pcint15 pcint14 pcint13 pcint12 pcint11 pcint10 pcint9 pcint8 pcmsk1 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 (0x6b) pcint7 pcint6 pcint5 pcint4 pcint3 pcint2 pcint1 pcint0 pcmsk0 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 57 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 14. i/o-ports 14.1 overview all avr ? ports have true read-modify- write functionality when used as general digita l i/o ports. this means that the direction of one port pin can be changed without uni ntentionally changing the direction of any other pin with the sbi and cbi instructions. the same applies when changing drive value (if configured as output) or enabling/ disabling of pull-up resistors (if configured as input). each output buffer has symmetrical dr ive characteristics with both high sink and source capability. the pin driver is strong enough to drive le d displays directly. all port pins have individually selectable pull-up resistors wi th a supply-voltage invariant re sistance. all i/o pins have protection diodes to both v cc and ground as indicated in figure 14-1 . refer to section 28. ?electrical char acteristics? on page 287 for a complete list of parameters. figure 14-1. i/o pin equivalent schematic all registers and bit references in this section are written in general form. a lower case ?x? represents the numbering letter for the port, and a lower case ?n? represents the bit number. howeve r, when using the register or bit defines in a program, the precise form must be used. for example, portb3 for bit no. 3 in port b, here documented generally as portxn. the physical i/o registers and bit locations are listed in section 14.4 ?register description? on page 72 . three i/o memory address locations are allocated for each po rt, one each for the data register ? portx, data direction register ? ddrx, and the port input pins ? pi nx. the port input pins i/o location is read only, while the data register and the data direction register are read/write. howeve r, writing a logic one to a bit in the pinx register, will result in a toggle in the corresponding bit in the data register. in addition, the pull-up disable ? pud bit in mcucr disables the pull-up function for a ll pins in all ports when set. using the i/o port as general digital i/o is described in section 14.2 ?ports as general digital i/o? on page 58 . most port pins are multiplexed with alternate functions for the peripheral features on the device. how each alternate functi on interferes with the port pin is described in section 14.3 ?alternate port functions? on page 62 . refer to the individual module sections for a full description of the alternate functions. no te that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital i/o. c pin r pu pxn logic see figure general digital i/o for details atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 58 14.2 ports as general digital i/o the ports are bi-directional i/o port s with optional internal pull-ups. figure 14-2 shows a functional description of one i/o-port pin, here generically called pxn. figure 14-2. general digital i/o (1) note: 1. wrx, wpx, wdx, rrx, rpx, and rdx are common to all pins within the same port. clk i/o , sleep, and pud are common to all ports. d 0 1 q wrx rrx wpx pxn clr reset synchronizer data bus portxn q q l d q q d q pinxn reset rpx wdx: write ddrx wrx: wpx: rpx: rrx: read portx register read portx pin write portx register rdx: write portx read ddrx pud: pullup disable clk i/o : sleep: i/o clock sleep control rdx clk i/o pud wdx sleep d q clr ddxn q 59 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 14.2.1 configuring the pin each port pin consists of three register bits: ddxn, portxn, and pinxn. as shown in section 14.4 ?register description? on page 72 , the ddxn bits are accessed at the d drx i/o address, the portxn bits at the portx i/o address, and the pinxn bits at the pinx i/o address. the ddxn bit in the ddrx register selects th e direction of this pin. if ddxn is writte n logic one, pxn is configured as an outp ut pin. if ddxn is written logic zero, px n is configured as an input pin. if portxn is written logic one when the pin is configured as an input pin, the pull-up resistor is activated. to switch the pull-up resistor off, portxn has to be written logic zero or the pin has to be configured as an output pin. the port pins are tri-stated when reset condition becomes active, even if no clocks are running. if portxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). if portxn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero). 14.2.2 toggling the pin writing a logic one to pinxn toggles the value of portxn, independent on the value of ddrxn. note that the sbi instruction can be used to toggle one single bit in a port. 14.2.3 switching between input and output when switching between tri-state ({ddxn, portxn} = 0b00) and output high ({ddxn, portxn} = 0b11), an intermediate state with either pull-up enabled {ddxn, portxn} = 0b01) or output low ({ddxn, portxn} = 0 b10) must occur. normally, the pull-up enabled state is fully acceptable, as a high-impedant environment will not noti ce the difference between a strong high driver and a pull-up. if this is not the case, the pud bit in the mcucr register can be set to disable all pull-ups in all port s. switching between input with pull-up and out put low generates the same problem. th e user must use ei ther the tri-state ({ddxn, portxn} = 0b00) or the out put high state ({ddxn, portxn} = 0b11) as an intermediate step. table 14-1 summarizes the control signals for the pin value. 14.2.4 reading the pin value independent of the setting of data direct ion bit ddxn, the port pin can be read thro ugh the pinxn register bit. as shown in figure 14-2 on page 58 , the pinxn register bit and the preceding latch co nstitute a synchronizer. this is needed to avoid metastability if the physical pin changes value near the edge of the internal clock, but it also introduces a delay. figure 14-3 on page 60 shows a timing diagram of the synchronization when reading an externally applied pin value. the maximum and minimum propagation delays are denoted t pd,max and t pd,min respectively. table 14-1. port pin configurations ddxn portxn pud (in mcucr) i/o pull-up comment 0 0 x input no tri-state (hi-z) 0 1 0 input yes pxn will source current if ext. pulled low. 0 1 1 input no tri-state (hi-z) 1 0 x output no output low (sink) 1 1 x output no output high (source) atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 60 figure 14-3. synchronization when reading an externally applied pin value consider the clock period starting shortl y after the first fallin g edge of the system cl ock. the latch is closed when the clock is low, and goes transparent when the clock is high, as indicate d by the shaded region of the ?sync latch? signal. the signal value is latched when the system clock goes low. it is clocked into the pinxn regist er at the succeeding positive clock edge. as indicated by the two arrows tpd,max and tpd,min, a sing le signal transition on the pin will be delayed between ? and 1? system clock period depending upon the time of assertion. when reading back a software assigned pin value, a n op instruction must be inserted as indicated in figure 14-4 . the out instruction sets the ?sync latch? signal at the positive edge of the clock. in this case, the delay tpd through the synchronizer is 1 system clock period. figure 14-4. synchronization when reading a software assigned pin value system clk instructios sync latch pinxn r17 xxx xxx 0x00 0xff in r17, pinx t pd, max t pd, min system clk instructios sync latch pinxn r16 r17 out portx, r16 nop 0x00 0xff 0xff in r17, pinx t pd 61 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 the following code example shows how to set port b pins 0 and 1 high, 2 and 3 low, and define the port pins from 4 to 7 as input with pull-ups assigned to port pins 6 and 7. the resulting pin values are read back again, but as previously discussed, a nop instruction is included to be able to read ba ck the value recently assigned to some of the pins. note: 1. for the assembly program, two temporary registers are used to minimize the time from pull-ups are set on pins 0, 1, 6, and 7, until the direction bits are correctly se t, defining bit 2 and 3 as low and redefining bits 0 and 1 as strong high drivers. 14.2.5 digital input enable and sleep modes as shown in figure 14-2 on page 58 , the digital input signal can be clamped to ground at the input of the schmitt-trigger. the signal denoted sleep in the figure, is se t by the mcu sleep controll er in power-down mode, po wer-save mode, and standby mode to avoid high power consumption if some input signals ar e left floating, or have an analog signal level close to v cc /2. sleep is overridden for port pins enabled as external interrupt pins. if the external interrupt request is not enabled, sleep is active also for these pins. sleep is also overridden by various other alternate functions as described in section 14.3 ?alternate port functions? on page 62 . if a logic high level (?one?) is present on an asynchronous extern al interrupt pin configured as ?interrupt on rising edge, fal ling edge, or any logic change on pin? while the external interrupt is not enabled, the corresponding external interrupt flag will be set when resuming from the above mentioned sleep mode, as the clamping in these sleep mode produces the requested logic change. 14.2.6 unconnected pins if some pins are unused, it is recommend ed to ensure that these pins have a defined level. even though most of the digital inputs are disabled in the deep sleep modes as described ab ove, floating inputs should be avoided to reduce current consumption in all other modes where the digital in puts are enabled (reset, active mode and idle mode). the simplest method to ensure a defined level of an unused pin, is to enable the inte rnal pull-up. in this case, the pull-up wi ll be disabled during reset. if low power consumption during reset is important, it is re commended to use an external pull-up or pull-down. connecting unused pins directly to v cc or gnd is not recommended, since this may cause excessive currents if the pin is accidentally configured as an output. assembly code example (1) ... ; define pull-ups and set outputs high ; define directions for port pins ldi r16,(1< 63 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 table 14-2 summarizes the function of the overriding signals. the pin and port indexes from figure 14-5 on page 62 are not shown in the succeeding tables. the overriding signals are generat ed internally in the modules having the alternate function. the following subsections shortly describe the alternate functi ons for each port, and relate the overriding signals to the alternate function. refer to the alternat e function description for further details. 14.3.1 alternate functions of port a the port a pins with alternate functions are shown in table 14-3 . table 14-2. generic description of overri ding signals for alternate functions signal name full name description puoe pull-up override enable if this signal is set, the pull-up enable is controlled by the puov signal. if this signal is cleared, the pull-up is enabled when {ddxn, portxn, pud} = 0b010. puov pull-up override value if puoe is set, the pull-up is enabled /disabled when puov is set/cleared, regardless of the setting of the ddx n, portxn, and pud register bits. ddoe data direction override enable if this signal is set, the output driver enable is controlled by the ddov signal. if this signal is cleared, the output driver is enabled by the ddxn register bit. ddov data direction override value if ddoe is set, the output driver is enabled/disabled when ddov is set/cleared, regardless of the setting of the ddxn register bit. pvoe port value override enable if this signal is set and the output driver is enabled, the port value is controlled by the pvov signal. if pvoe is cleared, and the output driver is enabled, the port value is controlled by the portxn register bit. pvov port value override value if pvoe is set, the port value is set to pvov, regardless of the setting of the portxn register bit. ptoe port toggle override enable if ptoe is set, the portxn register bit is inverted. dieoe digital input enable override enable if this bit is set, the digital input enable is controlled by the dieov signal. if this signal is cleared, the digital i nput enable is determined by mcu state (normal mode, sleep mode). dieov digital input enable override value if dieoe is set, the digital input is enabled/disabled when dieov is set/cleared, regardless of the mcu state (normal mode, sleep mode). di digital input this is the digital input to alternate functions. in the figure, the signal is connected to the output of the schmit t trigger but before the synchronizer. unless the digital input is used as a clock source, the module with the alternate function will use its own synchronizer. aio analog input/output this is the analog input/output to/fro m alternate functions. the signal is connected directly to the pad, and can be used bi-directionally. table 14-3. port a pins alternate functions port pin alternate function pa7 adc7 (adc input channel 7) pcint7 (pin change interrupt 7) pa6 adc6 (adc input channel 6) pcint6 (pin change interrupt 6) pa5 adc5 (adc input channel 5) pcint5 (pin change interrupt 5) pa4 adc4 (adc input channel 4) pcint4 (pin change interrupt 4) pa3 adc3 (adc input channel 3) pcint3 (pin change interrupt 3) pa2 adc2 (adc input channel 2) pcint2 (pin change interrupt 2) pa1 adc1 (adc input channel 1) pcint1 (pin change interrupt 1) pa0 adc0 (adc input channel 0) pcint0 (pin change interrupt 0) atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 64 ? adc7:0/pcint7:0 ? port a, bit 7:0 adc7:0, analog to digital converter, channels 7:0. pcint7:0, pin change interrupt source 7:0: the pa7:0 pins can serve as external interrupt sources. table 14-4 and table 14-5 relate the alternate functions of port a to the overriding signals shown in figure 14-5 on page 62 . table 14-4. overriding signals for alternate functions in pa7:pa4 signal name pa7/adc7/pcint7 pa6/adc6/pcint6 pa5/adc5/pcint5 pa4/adc4/pcint4 puoe 0 0 0 0 puov 0 0 0 0 ddoe 0 0 0 0 ddov 0 0 0 0 pvoe 0 0 0 0 pvov 0 0 0 0 dieoe pcint7 pcie0 + adc7d pcint6 pcie0 + adc6d pcint5 pcie0 + adc5d pcint4 pcie0 + adc4d dieov pcint7 pcie0 pcint6 pcie0 pcint5 pcie0 pcint4 pcie0 di pcint7 input pcint6 input pcint5 input pcint4 input aio adc7 input adc6 input adc5 input adc4 input table 14-5. overriding signals for alternate functions in pa3:pa0 signal name pa3/adc3/pcint3 pa2/adc2/pcint2 pa1/adc1/pcint1 pa0/adc0/pcint0 puoe 0 0 0 0 puov 0 0 0 0 ddoe 0 0 0 0 ddov 0 0 0 0 pvoe 0 0 0 0 pvov 0 0 0 0 dieoe pcint3 pcie0 + adc3d pcint2 pcie0 + adc2d pcint1 pcie0 + adc1d pcint0 pcie0 + adc0d dieov pcint3 pcie0 pcint2 pcie0 pcint1 pcie0 pcint0 pcie0 di pcint3 input pcint2 input pcint1 input pcint0 input aio adc3 input adc2 input adc1 input adc0 input 65 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 14.3.2 alternate functions of port b the port b pins with alternate functions are shown in table 14-6 . the alternate pin configuration is as follows: ? sck/oc3b/pcint15 ? port b, bit 7 sck: master clock output, slave clock input pin for spi channel. wh en the spi is enabled as a slave, this pin is configured as an input regardless of the setting of ddb7. when the spi0 is enabl ed as a master, the data direct ion of this pin is controlled by ddb7. when the pin is forced to be an input, th e pull-up can still be cont rolled by the portb7 bit. oc3b, output compare match b output: the pb7 pin can serv e as an external output fo r the timer/counter3 output compare. the pin has to be configured as an output (ddb7 set ?one?) to serve this fu nction. the oc3b pin is also the output pin for the pwm mode timer function. pcint15, pin change interrupt source 15: the pb7 pin can serve as an external interrupt source. ? miso/oc3a/pcint14 ? port b, bit 6 miso: master data input, slave data output pin for spi channel. when the spi is enabled as a master, this pin is configured as an input regardless of the setting of ddb 6. when the spi is enabled as a slave, th e data direction of this pin is controlled by ddb6. when the pin is forced to be an input, th e pull-up can still be cont rolled by the portb6 bit. oc3a, output compare match a output: the pb6 pin can serv e as an external output fo r the timer/counter0 output compare. the pin has to be configured as an output (ddb6 set ?one?) to serve this fu nction. the oc3a pin is also the output pin for the pwm mode timer function. pcint14, pin change interrupt source 14: the pb6 pin can serve as an external interrupt source. table 14-6. port b pins alternate functions port pin alternate functions pb7 sck (spi bus master clock input) oc3b (timer/counter 3 output compare match b output) pcint15 (pin change interrupt 15) pb6 miso (spi bus master input/slave output) oc3a (timer/counter 3 output compare match a output) pcint14 (pin change interrupt 14) pb5 mosi (spi bus master output/slave input) icp3 (timer/counter3 input capture trigger) pcint13 (pin change interrupt 13) pb4 ss (spi slave select input) oc0b (timer/counter 0 output compare match b output) pcint12 (pin change interrupt 12) pb3 ain1 (analog comparator negative input) oc0a (timer/counter 0 output compare match a output) pcint11 (pin change interrupt 11) pb2 ain0 (analog comparator positive input) int2 (external interrupt 2 input) pcint10 (pin change interrupt 10) pb1 t1 (timer/counter 1 external counter input) clko (divided system clock output) pcint9 (pin change interrupt 9) pb0 t0 (timer/counter 0 external counter input) xck0 (usart0 external clock input/output) pcint8 (pin change interrupt 8) atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 66 ? mosi/icp3/pcint13 ? port b, bit 5 mosi: spi master data output, slave data input for spi channel. wh en the spi is enabled as a slav e, this pin is configured as an input regardless of the setting of ddb5. when the spi is enabled as a master, the data direction of this pin is controlled by ddb5. when the pin is fo rced to be an input, the pull-up can still be controlled by the portb5 bit. icp3, input capture pin 3: the pb5 pin can ac t as an input capture pin for timer/counter3. pcint13, pin change interrupt source 13: the pb5 pin can serve as an external interrupt source. ?ss /oc0b/pcint12 ? port b, bit 4 ss : slave port select input. when the spi is enabled as a slave, this pin is configured as an input regardless of the setting of ddb4. as a slave, the spi is activated when this pin is dr iven low. when the spi is enabled as a master, the data direction of this pin is controlled by ddb4. when the pin is forced to be an input, the pull-up can still be controlled by the portb4 bit . oc0b, output compare match b output: the pb4 pin can serv e as an external output fo r the timer/counter0 output compare. the pin has to be configured as an output (ddb4 set ?one?) to serve this fu nction. the oc0b pin is also the output pin for the pwm mode timer function. pcint12, pin change interrupt source 12: the pb4 pin can serve as an external interrupt source. ? ain1/oc0a/pcint11, bit 3 ain1, analog comparator negative input. this pin is directly connected to the negative input of the analog comparator. oc0a, output compare match a output: the pb3 pin can serv e as an external output fo r the timer/counter0 output compare. the pin has to be configured as an output (ddb3 set ?one?) to serve this fu nction. the oc0a pin is also the output pin for the pwm mode timer function. pcint11, pin change interrupt source 11: the pb3 pin can serve as an external interrupt source. ? ain0/int2/pcint10, bit 2 ain0, analog comparator positiv e input. this pin is directly connected to the positive input of the analog comparator. int2, external interrupt source 2. the pb2 pin can serve as an external interrupt source to the mcu. pcint10, pin change interrupt source 10: the pb2 pin can serve as an external interrupt source. ? t1/clko/pcint9, bit 1 t1, timer/counter1 counter source. clko, divided system clock: the divided system clock can be out put on the pb1 pin. the divi ded system clock will be output if the ckout fuse is programmed, regardless of the port b1 and ddb1 settings. it will also be output during reset. pcint9, pin change interrupt source 9: the pb1 pin can serve as an external interrupt source. ? t0/xck0/pcint8, bit 0 t0, timer/counter0 counter source. xck0, usart0 external clock. the data direction register (ddb 0) controls whether the clock is output (ddd0 set ?one?) or input (ddd0 cleared). the xck0 pin is active onl y when the usart0 operates in synchronous mode. pcint8, pin change interrupt source 8: the pb0 pin can serve as an external interrupt source. 67 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 table 14-7 and table 14-8 relate the alternate functions of port b to the overriding signals shown in figure 14-5 on page 62 . spi mstr input and spi slave output consti tute the miso signal, while mosi is divided into spi mstr output and spi slave input. table 14-7. overriding signals for alternate functions in pb7:pb4 signal name pb7/sck/pcint15 pb6/miso/pcint14 pb5/mosi/pcint13 pb4/ss /oc0b/pcint12 puoe spe mstr spe mstr spe mstr spe mstr puov portb7 pud portb14 pud portb13 pud portb12 pud ddoe spe mstr spe mstr spe mstr spe mstr ddov 0 0 0 0 pvoe spe mstr spe mstr spe mstr oc0a enable pvov sck output spi slave output spi mstr output oc0a dieoe pcint15 pcie1 pcint14 pcie1 pcint13 pcie1 pcint12 pcie1 dieov 1 1 1 1 di sck input pcint17 input spi mstr input pcint14 input spi slave input pcint13 input spi ss pcint12 input aio ? ? ? ? table 14-8. overriding signals for alternate functions in pb3:pb0 signal name pb3/ain1/oc0b/pcint11 pb2/ain0/int2/pcint10 pb1/t1/clko/pcint9 pb0/t0/xck/pcint8 puoe 0 0 0 0 puov 0 0 0 0 ddoe 0 0 ckout 0 ddov 0 0 ckout 0 pvoe oc0b enable 0 ckout 0 pvov oc0b 0 clk i/o 0 dieoe pcint11 pcie1 int2 enable pcint10 pcie1 pcint9 pcie1 pcint8 pcie1 dieov 1 1 1 1 di pcint11 input int2 input pcint10 input t1 input pcint9 input t0 input pcint8 input aio ain1 input ain0 input ? ? atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 68 14.3.3 alternate functions of port c the port c pins with alter nate functions are shown in table 14-9 . ? tosc2/pcint23 ? port c, bit7 tosc2, timer oscillator pin 2. the pc7 pin can se rve as an external interr upt source to the mcu. pcint23, pin change interrupt source 23: the pc7 pin can serve as an external interrupt source. ? tosc1/pcint22 ? port c, bit 6 tosc1, timer oscillator pin 1. the pc6 pin can se rve as an external interr upt source to the mcu. pcint22, pin change interrupt source 22: the pc6 pin can serve as an external interrupt source. ? tdi/pcint21 ? port c, bit 5 tdi, jtag test data input. pcint21, pin change interrupt source 21: the pc5 pin can serve as an external interrupt source. ? tdo/pcint20 ? port c, bit 4 tdo, jtag test data output. pcint20, pin change interrupt source 20: the pc4 pin can serve as an external interrupt source. ? tms/pcint19 ? port c, bit 3 tms, jtag test mode select. pcint19, pin change interrupt source 19: the pc3 pin can serve as an external interrupt source. ? tck/pcint18 ? port c, bit 2 tck, jtag test clock. pcint18, pin change interrupt source 18: the pc2 pin can serve as an external interrupt source. ? sda/pcint17 ? port c, bit 1 sda, 2-wire serial bus data input/output line. pcint17, pin change interrupt source 17: the pc1 pin can serve as an external interrupt source. table 14-9. port c pins alternate functions port pin alternate function pc7 tosc2 (timer oscillator pin 2) pcint23 (pin change interrupt 23) pc6 tosc1 (timer oscillator pin 1) pcint22 (pin change interrupt 22) pc5 tdi (jtag test data input) pcint21 (pin change interrupt 21) pc4 tdo (jtag test data output) pcint20 (pin change interrupt 20) pc3 tms (jtag test mode select) pcint19 (pin change interrupt 19) pc2 tck (jtag test clock) pcint18 (pin change interrupt 18) pc1 sda (2-wire serial bus data input/output line) pcint17 (pin change interrupt 17) pc0 scl (2-wire serial bus clock line) pcint16 (pin change interrupt 16) 69 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 ? scl/pcint16 ? port c, bit 0 scl, 2-wire serial bus clock line. pcint16, pin change interrupt source 16: the pc0 pin can serve as an external interrupt source. table 14-10 and table 14-11 relate the alternate functions of port c to the overriding signals shown in figure 14-5 on page 62 . table 14-10. overriding signals for alternate functions in pc7:pc4 signal name pc7/tosc2/pcint23 pc6/tosc1/pcint22 pc5/tdi/pcint21 pc4/tdo/pcint20 puoe as2 exclk as2 jtagen jtagen puov 0 0 1 1 ddoe as2 exclk as2 jtagen jtagen ddov 0 0 0 shift_ir + shift_dr pvoe 0 0 0 jtagen pvov 0 0 0 tdo dieoe as2 exclk + pcint23 pcie2 as2 + pcint22 pcie2 jtagen + pcint21 pcie2 jtagen + pcint20 pcie2 dieov as2 exclk + as2 jtagen jtagen di pcint23 input pcint22 input pcint21 input pcint20 input aio t/c2 osc output t/c2 osc input tdi input ? table 14-11. overriding signals for alternate functions in pc3:pc0 signal name pc3/tms/pcint19 pc2/tck/pcint18 pc1/sda/pcint17 pc0/scl/pcint16 puoe jtagen jtagen twen twen puov 1 1 portc1 pud portc0 pud ddoe jtagen jtagen twen twen ddov 0 0 0 0 pvoe 0 0 twen twen pvov 0 0 sda out scl out dieoe jtagen + pcint19 pcie2 jtagen + pcint18 pcie2 pcint17 pcie2 pcint16 pcie2 dieov jtagen jtagen 1 1 di pcint19 input pcint18 input pcint17 input pcint16 input aio tms input tck input sda input scl input atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 70 14.3.4 alternate functions of port d the port d pins with alter nate functions are shown in table 14-12 . the alternate pin configuration is as follows: ? oc2a/pcint31 ? port d, bit 7 oc2a, output compare match a output: the pd7 pin can serve as an external output for the timer/counter2 output compare a. the pin has to be configured as an output (ddd7 set (one )) to serve this function. the oc2a pin is also the output pin for the pwm mode timer function. pcint31, pin change interrupt source 31:the pd7 pi n can serve as an external interrupt source. ? icp1/oc2b/pcint30 ? port d, bit 6 icp1, input capture pin 1: the pd6 pin can ac t as an input capture pin for timer/counter1. oc2b, output compare match b output: the pd6 pin can serve as an external output for the timer/counter2 output compare b. the pin has to be configured as an output (ddd6 set (one )) to serve this function. the oc2b pin is also the output pin for the pwm mode timer function. pcint30, pin change interrupt source 30: the pd6 pin can serve as an external interrupt source. ? oc1a/pcint29 ? port d, bit 5 oc1a, output compare match a output: the pd5 pin can serve as an external output for the timer/counter1 output compare a. the pin has to be configured as an output (ddd5 set (one )) to serve this function. the oc1a pin is also the output pin for the pwm mode timer function. pcint29, pin change interrupt source 29: the pd5 pin can serve as an external interrupt source. table 14-12. port d pins alternate functions port pin alternate function pd7 oc2a (timer/counter2 output compare match a output) pcint31 (pin change interrupt 31) pd6 icp1 (timer/counter1 in put capture trigger) oc2b (timer/counter2 output compare match b output) pcint30 (pin change interrupt 30) pd5 oc1a (timer/counter1 output compare match a output) pcint29 (pin change interrupt 29) pd4 oc1b (timer/counter1 output compare match b output) xck1 (usart1 external clock input/output) pcint28 (pin change interrupt 28) pd3 int1 (external interrupt1 input) txd1 (usart1 transmit pin) pcint27 (pin change interrupt 27) pd2 int0 (external interrupt0 input) rxd1 (usart1 receive pin) pcint26 (pin change interrupt 26) pd1 txd0 (usart0 transmit pin) pcint25 (pin change interrupt 25) pd0 rxd0 (usart0 receive pin) pcint24 (pin change interrupt 24) t3 (timer/counter 3 external counter input) 71 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 ? oc1b/xck1/pcint28 ? port d, bit 4 oc1b, output compare match b output: the pb4 pin can serv e as an external output fo r the timer/counter1 output compare b. the pin has to be configured as an output (ddd4 set (one )) to serve this function. the oc1b pin is also the output pin for the pwm mode timer function. xck1, usart1 external clock. the data direction register (ddb 4) controls whether the clock is output (ddd4 set ?one?) or input (ddd4 cleared). the xck4 pin is active onl y when the usart1 operates in synchronous mode. pcint28, pin change interrupt source 28: the pd4 pin can serve as an external interrupt source. ? int1/txd1/pcint27 ? port d, bit 3 int1, external interrupt source 1. the pd3 pin can serve as an external interrupt source to the mcu. txd1, transmit data (data output pin for the usart1). when the usart1 transmitte r is enabled, this pin is configured as an output regardless of the value of ddd3. pcint27, pin change interrupt source 27: the pd3 pin can serve as an external interrupt source. ? int0/rxd1/pcint26 ? port d, bit 2 int0, external interrupt source 0. the pd2 pin can serve as an external interrupt source to the mcu. rxd1, rxd0, receive data (data input pin for the usart1). when the usart1 receiver is enabled this pin is configured as an input regardless of the value of ddd2. when the usart forces this pin to be an input, the pull-up can still be controlled by the portd2 bit. pcint26, pin change interrupt source 26: the pd2 pin can serve as an external interrupt source. ? txd0/pcint25 ? port d, bit 1 txd0, transmit data (data output pin for the usart0). when the usart0 transmitte r is enabled, this pin is configured as an output regardless of the value of ddd1. pcint25, pin change interrupt source 25: the pd1 pin can serve as an external interrupt source. ? rxd0/t3/pcint24 ? port d, bit 0 rxd0, receive data (data input pin for the usart0). when the usart0 receiver is enabled this pin is configured as an input regardless of the value of ddd0. when the usart forces th is pin to be an input, the pull-up can still be controlled by the portd0 bit. t3, timer/counter3 counter source. pcint24, pin change interrupt source 24: the pd0 pin can serve as an external interrupt source. table 14-13 on page 72 and table 14-14 on page 72 relate the alternate functions of port d to the overriding signals shown in figure 14-5 on page 62 . atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 72 14.4 register description 14.4.1 mcucr ? mcu control register ? bit 4 ? pud: pull-up disable when this bit is written to one, the pull-ups in the i/o po rts are disabled even if the ddxn and portxn registers are configured to enable the pull-ups ({ddxn, portxn} = 0b01). see section 14.2.1 ?configuring the pin? on page 59 for more details about this feature. table 14-13. overriding signals fo r alternate functions pd7:pd4 signal name pd7/oc2a/pcint31 pd6/icp1/oc2b/pcint30 pd5/oc1a/pcint29 pd4/oc1b/xck1/pcint28 puoe 0 0 0 0 puov 0 0 0 0 ddoe 0 0 0 0 ddov 0 0 0 0 pvoe oc2a enable oc2b enable oc1a enable oc1b enable pvov oca2a oc2b oc1a oc1b dieoe pcint31 pcie3 pcint30 pcie3 pcint29 pcie3 pcint28 pcie3 dieov 1 1 1 1 di pcint31 input icp1 input pcint30 input pcint29 input pcint28 input aio ? ? ? ? table 14-14. overriding signals for alternate functions in pd3:pd0 (1) signal name pd3/int1/txd1/pcint27 pd2/int0/rxd1/pcint26 pd1/txd0/pcint25 pd0/rxd0/pcint27 puoe txen1 rxen1 txen0 rxen1 puov 0 portd2 pud 0 portd0 pud ddoe txen1 rxen1 txen0 rxen1 ddov 1 0 1 0 pvoe txen1 0 txen0 0 pvov txd1 0 txd0 0 dieoe int1 enable pcint27 pcie3 int2 enable pcint26 pcie3 pcint25 pcie3 pcint24 pcie3 dieov 1 1 1 1 di int1 input pcint27 input int0 inputrxd1 pcint26 input pcint25 input rxd0pcint24 input aio ? ? ? ? note: 1. when enabled, the 2-wire serial interface enables slew-r ate controls on the output pins pd0 and pd1. this is not shown in this table. in additi on, spike filters are connected between the aio outputs shown in the port figure and the digital logic of the twi module. bit 7 6 5 4 3 2 1 0 0x35 (0x55) jtd bods bodse pud ? ? ivsel ivce mcucr read/write r/w r/w r/w r/w r r r/w r/w initial value 0 0 0 0 0 0 0 0 73 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 14.4.2 porta ? port a data register 14.4.3 ddra ? port a data direction register 14.4.4 pina ? port a input pins address 14.4.5 portb ? port b data register 14.4.6 ddrb ? port b data direction register 14.4.7 pinb ? port b input pins address 14.4.8 portc ? port c data register bit 76543210 0x02 (0x22) porta7 porta6 porta5 porta4 porta3 porta2 porta1 porta0 porta read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 0x01 (0x21) dda7 dda6 dda5 dda4 dda3 dda2 dda1 dda0 ddra read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 0x00 (0x20) pina7 pina6 pina5 pina4 pina3 pina2 pina1 pina0 pina read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value n/a n/a n/a n/a n/a n/a n/a n/a bit 76543210 0x05 (0x25) portb7 portb6 portb5 port b4 portb3 portb2 portb1 portb0 portb read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 0x04 (0x24) ddb7 ddb6 ddb5 ddb4 ddb3 ddb2 ddb1 ddb0 ddrb read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 0x03 (0x23) pinb7 pinb6 pinb5 pinb4 pinb3 pinb2 pinb1 pinb0 pinb read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value n/a n/a n/a n/a n/a n/a n/a n/a bit 76543210 0x08 (0x28) portc7 portc6 portc5 port c4 portc3 portc2 portc1 portc0 portc read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 74 14.4.9 ddrc ? port c data direction register 14.4.10 pinc ? port c input pins address 14.4.11 portd ? port d data register 14.4.12 ddrd ? port d data direction register 14.4.13 pind ? port d input pins address bit 76543210 0x07 (0x27) ddc7 ddc6 ddc5 ddc4 ddc3 ddc2 ddc1 ddc0 ddrc read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 0x06 (0x26) pinc7 pinc6 pinc5 pinc4 pinc3 pinc2 pinc1 pinc0 pinc read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value n/a n/a n/a n/a n/a n/a n/a n/a bit 76543210 0x0b (0x2b) portd7 portd6 portd5 port d4 portd3 portd2 portd1 portd0 portd read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 0x0a (0x2a) ddd7 ddd6 ddd5 ddd4 ddd3 ddd2 ddd1 ddd0 ddrd read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 0x09 (0x29) pind7 pind6 pind5 pind4 pind3 pind2 pind1 pind0 pind read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value n/a n/a n/a n/a n/a n/a n/a n/a 75 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 15. 8-bit timer/counter0 with pwm 15.1 features two independent output compare units double buffered out put compare registers clear timer on compare match (auto reload) glitch free, phase correct pulse width modulator (pwm) variable pwm period frequency generator three independent interrupt sources (tov0, ocf0a, and ocf0b) 15.2 overview timer/counter0 is a general purpose 8-bit timer/counter mo dule, with two independent output compare units, and with pwm support. it allows accurate program execution timing (event management) and wave generation. a simplified block diagram of the 8-bit timer/counter is shown in figure 15-1 . for the actual placement of i/o pins, see section 1. ?pin configurations? on page 3 . cpu accessible i/o registers, including i/o bits and i/o pins, are shown in bold. the device-specific i/o register and bit locations are listed in the section 15.9 ?register description? on page 85 . figure 15-1. 8-bit timer/counter block diagram control logic tcntn timer/counter count clear direction clk tn ocrna ocrnb tccrna tccrnb = edge detector (from prescaler) clock select top bottom tovn (int. req.) ocna (int. req.) tn waveform generation fixed top value data bus = = = 0 ocna ocnb (int. req.) waveform generation ocnb atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 76 15.2.1 registers the timer/counter (tcnt0) and output compare registers (o cr0a and ocr0b) are 8-bit registers. interrupt request (abbreviated to int.req. in the figure) signals are all visible in the timer interrupt flag register (tifr0). all interrupts ar e individually masked with the timer inte rrupt mask register (timsk0). tifr0 and timsk0 are not shown in the figure. the timer/counter can be clocked internally, via the prescaler, or by an external clock source on the t0 pin. th e clock select logic block controls which clock source and edge the timer/ counter uses to increment (o r decrement) its value. the timer/counter is inactive when no clock source is selected. the out put from the clock select logic is referred to as the timer clock (clk t0 ). the double buffered output compare registers (ocr0a and ocr0b) are compared with the timer/counter value at all times. the result of the compare can be used by the waveform generator to generate a pwm or variable frequency output on the output compare pins (oc0a and oc0b). section 15.5 ?output compare unit? on page 77 for details. the compare match event will also set the compare flag (ocf 0a or ocf0b) which can be used to ge nerate an output compare interrupt request. 15.2.2 definitions many register and bit references in this section are written in general form. a lower case ?n? replaces the timer/counter number, in this case 0. a lower case ?x? replaces the output compare unit, in this case compare unit a or compare unit b. however, when using the register or bit defines in a progr am, the precise form must be used, i.e., tcnt0 for accessing timer/counter0 counter value and so on. the definitions in table 15-1 are also used extensively throughout the document. 15.3 timer/counter clock sources the timer/counter can be clocked by an internal or an extern al clock source. the clock sour ce is selected by the clock select logic which is controlled by the clock select (cs02:0) bi ts located in the timer/counter control register (tccr0b). for details on clock source s and prescaler, see section 17.10 ?timer/counter prescaler? on page 131 . 15.4 counter unit the main part of the 8-bit timer/counter is the programmable bi-directional counter unit. figure 15-2 shows a block diagram of the counter and its surroundings. figure 15-2. counter unit block diagram table 15-1. definitions parameter definition bottom the counter reaches the bott om when it becomes 0x00. max the counter reaches its maximum when it becomes 0xff (decimal 255). top the counter reaches the top when it becomes equa l to the highest value in the count sequence. the top value can be assigned to be the fixed value 0xff (max) or the value stored in the ocr0a register. the assignment is dependent on the mode of operation. top bottom tovn (int. req.) data bus control logic tcntn clk tn clear count direction edge detector (from prescaler) clock select tn 77 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 signal description (internal signals): count increment or decrement tcnt0 by 1. direction select between increment and decrement. clear clear tcnt0 (set all bits to zero). clk t n timer/counter clock, referred to as clk t0 in the following. top signalize that tcnt0 has reached maximum value. bottom signalize that tcnt0 has reached minimum value (zero). depending of the mode of operation used, the counter is clea red, incremented, or decreme nted at each timer clock (clk t0 ). clk t0 can be generated from an external or internal clock source , selected by the clock select bits (cs02:0). when no clock source is selected (cs02:0 = 0) the time r is stopped. however, the tcnt0 value can be accessed by the cpu, regardless of whether clk t0 is present or not. a cpu write overrides (has pr iority over) all counter clear or count operations. the counting sequence is determined by the setting of the wgm01 and wgm00 bits located in the timer/counter control register (tccr0a) and the wgm02 bit located in the timer/counter control register b (tccr0b). there are close connections between how the counter behaves (counts) and ho w waveforms are generated on the output compare outputs oc0a and oc0b. for more details about advanced counting sequences and waveform generation, see section 15.7 ?modes of operation? on page 79 . the timer/counter overflow flag (tov0) is set according to t he mode of operation selected by the wgm02:0 bits. tov0 can be used for generating a cpu interrupt. 15.5 output compare unit the 8-bit comparator continuously compares tcnt0 with the output compare register s (ocr0a and ocr0b). whenever tcnt0 equals ocr0a or ocr0b, the comparator signals a ma tch. a match will set the outpu t compare flag (ocf0a or ocf0b) at the next timer clo ck cycle. if the corresponding interrupt is enabled , the output compare fl ag generates an output compare interrupt. the output compare flag is automatically cleared when the interrupt is executed. alternatively, the flag can be cleared by software by writing a logical one to its i/o bit location. the waveform generator uses the match signal to generate an output according to operating mode set by the wg m02:0 bits and compare output mode (com0x1:0) bits. the max and bottom signals are used by the waveform generator for handling the special cases of the extreme values in some modes of operation ( section 15.7 ?modes of operation? on page 79 ). figure 15-3 shows a block diagram of the output compare unit. figure 15-3. output comp are unit, block diagram ocfnx (int. req.) = (8-bit comparator) ocrnx waveform generator tcntn ocnx top bottom focn wgmn1:0 comnx1:0 data bus atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 78 the ocr0x registers are double buffered when using any of the pulse width modulation (pwm) modes. for the normal and clear timer on compare (ctc) modes of operation, the doubl e buffering is disabled. the double buffering synchronizes the update of the ocr0x compare registers to either top or bottom of the counting sequence. the synchronization prevents the occurrence of odd-length, non-symmetrical pwm pulses, thereby making the output glitch-free. the ocr0x register access may seem co mplex, but this is not case. when th e double buffering is enabled, the cpu has access to the ocr0x buffer register, and if double buffer ing is disabled the cpu will access the ocr0x directly. 15.5.1 force output compare in non-pwm waveform generation modes, the match output of the comparator can be forced by writing a one to the force output compare (foc0x) bit. forc ing compare match will not set the ocf0x flag or reload/clear the timer, but the oc0x pin will be updated as if a real compare match had occurred (the co m0x1:0 bits settings define w hether the oc0x pin is set, cleared or toggled). 15.5.2 compare match blocking by tcnt0 write all cpu write operations to the tcnt0 register will block any compare match t hat occur in the next timer clock cycle, even when the timer is stopped. this feature allows ocr0x to be initialized to the same value as tcnt0 without triggering an interrupt when the timer/counter clock is enabled. 15.5.3 using the ou tput compare unit since writing tcnt0 in any mode of ope ration will block all compare matches for one timer clock cycle, there are risks involved when changing tcnt0 when using the output compare unit, independently of whether the timer/counter is running or not. if the value written to tcnt0 equals the ocr0x value, the compare match will be missed, resulting in incorrect waveform generation. similarly, do not write the tcnt0 valu e equal to bottom when the counter is down-counting. the setup of the oc0x should be performed bef ore setting the data direction register for the port pin to output. the easiest way of setting the oc0x value is to use the force output co mpare (foc0x) strobe bits in normal mode. the oc0x registers keep their values even when changing between waveform generation modes. be aware that the com0x1:0 bits are not double buffered together with the compar e value. changing the com0x1:0 bits will take effect immediately. 15.6 compare match output unit the compare output mode (com0x1:0) bits have two functi ons. the waveform generator uses the com0x1:0 bits for defining the output compare (oc0x) state at the next compare match. also, the com0x1:0 bits control the oc0x pin output source. figure 15-4 on page 79 shows a simplified schematic of the logic affected by the com0x1:0 bit setting. the i/o registers, i/o bits, and i/o pins in the figure are shown in bold. only the pa rts of the general i/o port control regis ters (ddr and port) that are affected by the com0x1:0 bits are shown. when referri ng to the oc0x state, the reference is for the internal oc0x register, not the oc0x pin. if a system re set occur, the oc0x register is reset to ?0?. 79 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 figure 15-4. compare match output unit, schematic the general i/o port function is overridden by the output co mpare (oc0x) from the waveform generator if either of the com0x1:0 bits are set. however, the oc0x pin direction (input or output) is still controlled by the data direction register (ddr) for the port pin. the data direction register bit for the oc0x pin (ddr_oc 0x) must be set as output before the oc0x value is visible on the pin. the port override func tion is independent of the waveform generation mode. the design of the output compare pin logic allows initialization of the oc0x state before the output is enabled. note that some com0x1:0 bit settings are reserved for certain modes of operation. see section 15.9 ?register description? on page 85 . 15.6.1 compare output mode and waveform generation the waveform generator uses the com0x1:0 bits differentl y in normal, ctc, and pwm modes. for all modes, setting the com0x1:0 = 0 tells the waveform generator that no action on the oc0x register is to be performed on the next compare match. for compare output actions in the non-pwm modes refer to table 15-2 on page 85 . for fast pwm mode, refer to table 15-3 on page 85 , and for phase correct pwm refer to table 15-4 on page 85 . a change of the com0x1:0 bits state will have effect at the first compare match after the bi ts are written. for non-pwm modes, the action can be forced to have immedi ate effect by using the foc0x strobe bits. 15.7 modes of operation the mode of operation, i.e., t he behavior of the timer/counter and the output compare pins, is defined by the combination of the waveform generation mode (wgm02:0) and compare output mode (com0x1:0) bits. the compare output mode bits do not affect the counting sequence, while t he waveform generation mode bits do. the com0x1:0 bits control whether the pwm output generated should be inverted or not (inverted or non-inverted pwm). for non-p wm modes the com0x1:0 bits control whether the output should be set, clea red, or toggled at a compare match (see section 16.8 ?compare match output unit? on page 100 ). for detailed timing information see section 15.8 ?timer/counter timing diagrams? on page 83 . data bus 0 1 q d comnx1 comnx0 focn ocnx waveform generator q d port q d ddr ocnx pin clk i/o atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 80 15.7.1 normal mode the simplest mode of operation is t he normal mode (wgm02:0 = 0). in this mo de the counting direction is always up (incrementing), and no counter clear is performed. the coun ter simply overruns when it passes its maximum 8-bit value (top = 0xff) and then restarts from the bottom (0x00). in normal operation the ti mer/counter overflow flag (tov0) will be set in the same timer cl ock cycle as the tcnt0 becomes zero . the tov0 flag in this case behaves like a ninth bit, except that it is only set, not cleared. however, combined with the timer overflow interrupt that automatically clears the tov0 flag, the timer resolution can be increased by software. there are no special cases to consider in the normal mode, a new counter value can be written anytime. the output compare unit can be used to generate interrupts at some given time. using the output compare to generate waveforms in normal mode is not recommended, since this will occupy too much of the cpu time. 15.7.2 clear timer on compare match (ctc) mode in clear timer on compare or ctc mode (wgm02:0 = 2), the ocr0 a register is used to manipulate the counter resolution. in ctc mode the counter is cleared to zero when the counter value (tcnt0) matches the ocr0a. the ocr0a defines the top value for the counter, hence also its resolution. this mode allo ws greater control of the comp are match output frequency. it also simplifies the operation of counting external events. the timing diagram for the ctc mode is shown in figure 15-5 . the counter value (tcnt0) increases until a compare match occurs between tcnt0 and ocr0a, and then counter (tcnt0) is cleared. figure 15-5. ctc mode, timing diagram an interrupt can be generated each time the counter value reac hes the top value by using the ocf0a flag. if the interrupt is enabled, the interrupt handler routine can be used for updat ing the top value. however, changing top to a value close to bottom when the counter is running with non e or a low prescaler value must be done with care since the ctc mode does not have the double buffering feat ure. if the new value written to ocr0a is lower than the current value of tcnt0, the counter will miss the compare match. the counter will then have to count to its maximum value (0xff) and wrap around starting at 0x00 before the compare match can occur. for generating a waveform output in ctc mode, the oc0a output can be set to to ggle its logical level on each compare match by setting the compare output mode bits to toggle mode (com0a1:0 = 1). the oc0a value will not be visible on the port pin unless the data direction for the pin is set to out put. the waveform generated will have a maximum frequency of f oc0 = f clk_i/o /2 when ocr0a is set to zero (0x00). the waveform frequency is defined by the following equation: the n variable represents the prescale fa ctor (1, 8, 64, 256, or 1024). as for the normal mode of opera tion, the tov0 flag is set in the same timer clock cycle that the counter counts from max to 0x00. 12 tcntn (comnx1:0 = 1) ocnx (toggle) period 3 ocnx interrupt flag set 4 f ocnx f clk_i/o 2 n 1 ocrnx + () ?? ------------------------------------------------ - = 81 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 15.7.3 fast pwm mode the fast pulse width modulation or fast pwm mode (wgm02: 0 = 3 or 7) provides a high frequency pwm waveform generation option. the fast pwm differs from the other pwm optio n by its single-slope operation. the counter counts from bottom to top then restarts from bottom. top is defined as 0xff when wgm2:0 = 3, and ocr0a when wgm2:0 = 7. in non-inverting compare output mode, the output compare (oc0x) is cleared on the compare match between tcnt0 and ocr0x, and set at bottom. in inverting compare output mode, the output is set on compare match and cleared at bottom. due to the single-slope operatio n, the operating frequency of the fast pwm mode can be twice as high as the phase correct pwm mode that use dual-sl ope operation. this high frequency makes the fast pwm mode well suited for power regulation, rectification, and dac applications. high frequency allows physically small sized external components (coils, capacitors), and theref ore reduces total system cost. in fast pwm mode, the counter is incremen ted until the counter value ma tches the top value. the counter is then cleared at the following timer clock cycle. the timing diagram for the fast pwm mode is shown in figure 15-6 . the tcnt0 value is in the timing diagram shown as a histogram for illustrating the single-slope operation. the diagram includes non-inverted and inverted pwm outputs. the sm all horizontal line marks on the tcnt0 slopes represent compare matches between ocr0x and tcnt0. figure 15-6. fast pwm mode, timing diagram the timer/counter overflow flag (tov0) is set each time the co unter reaches top. if the inte rrupt is enabled, the interrupt handler routine can be used fo r updating the compare value. in fast pwm mode, the compare unit allows generation of pwm waveforms on the oc0x pins. setting the com0x1:0 bits to two will produce a non-inverted pwm and an inverted pwm out put can be generated by setti ng the com0x1:0 to three: setting the com0a1:0 bits to one allows the oc0a pin to toggl e on compare matches if the wgm0 2 bit is set. this option is not available for the oc0b pin (see table 15-3 on page 85 ). the actual oc0x value will only be visible on the port pin if the data direction for the port pin is set as output. the pwm waveform is generated by se tting (or clearing) the oc0x register at the compare match between ocr0x and tcnt 0, and clearing (or settin g) the oc0x register at the timer clock cycle the counter is cleared (changes from top to bottom). the pwm frequency for the output can be calculated by the following equation: the n variable represents the prescale fa ctor (1, 8, 64, 256, or 1024). the extreme values for the ocr0a register represents special cases when generating a pwm waveform output in the fast pwm mode. if the ocr0a is set equal to bottom, the output will be a narrow sp ike for each max+1 timer clock cycle. setting the ocr0a equal to max will result in a constantly high or low output (depending on the pol arity of the output set by the com0a1:0 bits.) 1234567 tcntn (comnx1:0 = 2) (comnx1:0 = 3) ocnx ocnx period ocrnx update and tovn interrupt flag set ocrnx interrupt flag set f ocnxpwm f clk_i/o n 256 ? ----------------- = atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 82 a frequency (with 50% duty cycle) waveform output in fast pw m mode can be achieved by settin g oc0x to togg le its logical level on each compare match (com0x1:0 = 1). the waveform generated will have a maximum frequency of f oc0 = f clk_i/o /2 when ocr0a is set to zero. this feature is similar to the oc 0a toggle in ctc mode, except the double buffer feature of the output compare unit is enabled in the fast pwm mode. 15.7.4 phase correct pwm mode the phase correct pwm mode (wgm02:0 = 1 or 5) provides a high resolution phase correct pwm waveform generation option. the phase correct pwm mode is based on a dual-slope operation. the counter count s repeatedly from bottom to top and then from top to bottom. top is defined as 0xff when wgm2:0 = 1, and ocr0a when wgm2:0 = 5. in non-inverting compare output mode, the output compare (oc0x) is cleared on the compare match between tcnt0 and ocr0x while upcounting, and set on the compare match while down-counting. in inverting output compare mode, the operation is inverted. the dual-slope operation has lowe r maximum operation frequency than single slope operation. however, due to the symmetric feature of the dual-slo pe pwm modes, these modes are preferred for motor control applications. in phase correct pwm mode the counter is incremented until the counter value matches top. when the counter reaches top, it changes the count direct ion. the tcnt0 value will be equal to top for one timer clock cycle. the timing diagram for the phase correct pwm mode is shown on figure 15-7 . the tcnt0 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. the diagram includes non- inverted and inverted pwm outputs. the small horizontal line marks on the tcnt0 slopes represent compare matches between ocr0x and tcnt0. figure 15-7. phase correct pwm mode, timing diagram the timer/counter overflow flag (tov0) is set each time the counter reaches bottom. the interrupt flag can be used to generate an interrupt each time the counter reaches the bottom value. in phase correct pwm mode, the compare unit allows ge neration of pwm waveforms on the oc0x pins. setting the com0x1:0 bits to two will produce a non-inverted pwm. an inverted pwm output can be generated by setting the com0x1:0 to three: setting the com0a0 bits to one allows the oc0a pin to toggle on compare matches if the wgm02 bit is set. this option is not available for the oc0b pin (see table 15-4 on page 85 ). the actual oc0x value will only be visible on the port pin if the data direction for the port pin is set as output. 123 tcntn (comnx1:0 = 2) (comnx1:0 = 3) ocnx ocnx period tovn interrupt flag set ocrnx update ocnx interrupt flag set 83 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 the pwm waveform is generated by clearing (or setting) th e oc0x register at the compare match between ocr0x and tcnt0 when the counter increments, and setting (or clearing) the oc0x register at com pare match between ocr0x and tcnt0 when the counter decrements. the pwm frequency for t he output when using phase co rrect pwm can be calculated by the following equation: the n variable represents the prescale factor (1, 8, 64, 256, or 1024). the extreme values for the ocr0a regist er represent special cases when generating a pwm waveform output in the phase correct pwm mode. if the ocr0a is set equal to bottom, the output will be continuously low and if set equal to max the output will be continuously high for no n-inverted pwm mode. for inverted pwm the output will have the opposite logic values. at the very start of period 2 in figure 15-7 on page 82 ocnx has a transition from high to low even though there is no compare match. the point of this transition is to guaran tee symmetry around bottom. there are two cases that give a transition without compare match. ocr0a changes its value from max, like in figure 15-7 on page 82 . when the ocr0a value is max the ocn pin value is the same as the result of a down-counting co mpare match. to ensure symmetry around bottom the ocn value at max must correspond to the re sult of an up-counting compare match. the timer starts counting from a value higher than the on e in ocr0a, and for that reason misses the compare match and hence the ocn change that would have happened on the way up. 15.8 timer/counter timing diagrams the timer/counter is a synchronous design and the timer clock (clk t0 ) is therefore shown as a clock enable signal in the following figures. the figures include inform ation on when interrupt flags are set. figure 15-8 contains timing data for basic timer/counter operation. the figure show s the count sequence close to the max value in all modes other than phase correct pwm mode. figure 15-8. timer/counter timing diagram, no prescaling f ocnxpcpwm f clk_i/o n 510 ? ----------------- = max - 1 clk i/o (clk i/o /1) tcntn tovn clk tn max bottom bottom + 1 atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 84 figure 15-9 shows the same timing data, but with the prescaler enabled. figure 15-9. timer/counter timing diagram, with prescaler (f clk_i/o /8) figure 15-10 shows the setting of ocf0b in all modes and ocf0a in all modes except ctc mode and pwm mode, where ocr0a is top. figure 15-10.timer/counter timing diagra m, setting of ocf0x, with prescaler (f clk_i/o /8) figure 15-11 shows the setting of ocf0a and the clearing of tcnt0 in ctc mode and fast pwm mode where ocr0a is top. figure 15-11.timer/counte r timing diagram, clear timer on co mpare match mode, with prescaler (f clk_i/o /8) max - 1 clk i/o (clk i/o /8) tcntn tovn clk tn max bottom bottom + 1 ocrnx - 1 clk i/o (clk i/o /8) tcntn ocrnx ocfnx clk tn ocrnx ocrnx + 1 ocrnx value ocrnx + 2 top - 1 clk i/o (clk i/o /8) tcntn (ctc) ocrnx ocfnx clk tn top bottom top bottom + 1 85 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 15.9 register description 15.9.1 tccr0a ? timer/counter control register a ? bits 7:6 ? com0a1:0: compare match output a mode these bits control the output compare pin (oc0a) behavior. if o ne or both of the com0a1:0 bits are set, the oc0a output overrides the normal port functionality of th e i/o pin it is connected to. however, not e that the data direction register (ddr) bit corresponding to the oc0a pin must be set in order to enable the output driver. when oc0a is connected to the pin, the function of the com0a1:0 bits depends on the wgm02:0 bit setting. table 15-2 shows the com0a1:0 bit functionality when the wgm 02:0 bits are set to a normal or ctc mode (non-pwm). table 15-3 shows the com0a1:0 bit functionality when the wgm01:0 bits are set to fast pwm mode. table 15-4 shows the com0a1:0 bit functionality when the wgm02:0 bits are set to phase correct pwm mode. bit 7 6 5 4 3 2 1 0 0x24 (0x44) com0a1 com0a0 com0b1 com0b0 ? ? wgm01 wgm00 tccr0a read/write r/w r/w r/w r/w r r r/w r/w initial value 0 0 0 0 0 0 0 0 table 15-2. compare output mode, non-pwm mode com0a1 com0a0 description 0 0 normal port operation, oc0a disconnected. 0 1 toggle oc0a on compare match 1 0 clear oc0a on compare match 1 1 set oc0a on compare match table 15-3. compare output mode, fast pwm mode (1) com0a1 com0a0 description 0 0 normal port operation, oc0a disconnected. 0 1 wgm02 = 0: normal port oper ation, oc0a disconnected. wgm02 = 1: toggle oc0a on compare match. 1 0 clear oc0a on compare match, set oc0a at bottom, (non-inverting mode). 1 1 set oc0a on compare match, clear oc0a at bottom, (inverting mode). note: 1. a special case occurs when ocr0a equals top and com0a1 is set. in this case, the compare match is ignored, but the set or clear is done at bottom. see section 15.7.3 ?fast pwm mode? on page 81 for more details. table 15-4. compare output mode, phase correct pwm mode (1) com0a1 com0a0 description 0 0 normal port operation, oc0a disconnected. 0 1 wgm02 = 0: normal port opera tion, oc0a disconnected. wgm02 = 1: toggle oc0a on compare match. 1 0 clear oc0a on compare match when up-counting. set oc0a on compare match when down-counting. 1 1 set oc0a on compare match when up-counting. clear oc0a on compare match when down-counting. note: 1. a special case occurs when ocr0a equals top and com0a1 is set. in this case, the compare match is ignored, but the set or clear is done at top. see section 15.7.4 ?phase correct pwm mode? on page 82 for more details. atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 86 ? bits 5:4 ? com0b1:0: compare match output b mode these bits control the output compare pin (oc0b) behavior. if o ne or both of the com0b1:0 bits are set, the oc0b output overrides the normal port functionality of th e i/o pin it is connected to. however, not e that the data direction register (ddr) bit corresponding to the oc0b pin must be set in order to enable the output driver. when oc0b is connected to the pin, the function of the com0b1:0 bits depends on the wgm02:0 bit setting. table 15-2 on page 85 shows the com0a1:0 bit functionality when the wgm02:0 bits are set to a normal or ctc mode (non-pwm). table 15-6 shows the com0b1:0 bit functionality when the wgm02:0 bits are set to fast pwm mode. table 15-7 shows the com0b1:0 bit functionality when the wgm02:0 bits are set to phase correct pwm mode. ? bits 3:2 ? reserved these bits are reserved bits in the atmega164p- b/324p-b/644p-b and will always read as zero. table 15-5. compare output mode, non-pwm mode com0b1 com0b0 description 0 0 normal port operation, oc0b disconnected. 0 1 toggle oc0b on compare match 1 0 clear oc0b on compare match 1 1 set oc0b on compare match table 15-6. compare output mode, fast pwm mode (1) com0b1 com0b0 description 0 0 normal port operation, oc0b disconnected. 0 1 reserved 1 0 clear oc0b on compare match, set oc0b at bottom, (non-inverting mode). 1 1 set oc0b on compare match, clear oc0b at bottom, (inverting mode). note: 1. a special case occurs when ocr0b equals top and com0b1 is set. in this case, the compare match is ignored, but the set or clear is done atbottom. see section 15.7.3 ?fast pwm mode? on page 81 for more details. table 15-7. compare output mode, phase correct pwm mode (1) com0b1 com0b0 description 0 0 normal port operation, oc0b disconnected. 0 1 reserved 1 0 clear oc0b on compare match when up-counting. set oc0b on compare match when down-counting. 1 1 set oc0b on compare match when up-counting. clear oc0b on compare match when down-counting. note: 1. a special case occurs when ocr0b equals top and com0b1 is set. in this case, the compare match is ignored, but the set or clear is done at top. see section 15.7.4 ?phase correct pwm mode? on page 82 for more details. 87 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 ? bits 1:0 ? wgm01:0: waveform generation mode combined with the wgm02 bit found in the t ccr0b register, these bits control the counting sequence of the counter, the source for maximum (top) counter value, and w hat type of waveform generation to be used, see table 15-8 . modes of operation supported by the timer/counter unit are: normal mode (counter), clear ti mer on compare match (ctc) mode, and two types of pulse width modulation (pwm) modes (see section 16.9 ?modes of operation? on page 101 ). 15.9.2 tccr0b ? timer/count er control register b ? bit 7 ? foc0a: force output compare a the foc0a bit is only active when the wgm bits specify a non-pwm mode. however, for ensuring compatibility with future devices, this bit must be set to zero when tccr0b is written when operating in pwm mode. when writing a logical one to the foc0a bi t, an immediate compare match is forced on the waveform generation unit. the oc0a output is changed according to its com0a1:0 bits setting. note that the foc0a bit is implemented as a strobe. therefor e it is the value present in the com0a1:0 bits that determ ines the effect of the forced compare. a foc0a strobe will not generate any interrupt, nor will it clear the timer in ctc mode using ocr0a as top. the foc0a bit is always read as zero. ? bit 6 ? foc0b: force output compare b the foc0b bit is only active when the wgm bits specify a non-pwm mode. however, for ensuring compatibility with future devices, this bit must be set to zero when tccr0b is written when operating in pwm mode. when writing a logical one to the foc0b bi t, an immediate compare match is forced on the waveform generation unit. the oc0b output is changed according to its com0b1:0 bits setting. note that the foc0b bit is implemented as a strobe. therefor e it is the value present in the com0b1:0 bits that determ ines the effect of the forced compare. a foc0b strobe will not generate any interrupt, nor will it clear the timer in ctc mode using ocr0b as top. the foc0b bit is always read as zero. ? bits 5:4 ? reserved these bits are reserved and will always read as zero. table 15-8. waveform generation mode bit description mode wgm2 wgm1 wgm0 timer/counter mode of operation top update of ocrx at tov flag set on (1)(2) 0 0 0 0 normal 0xff immediate max 1 0 0 1 pwm, phase correct 0xff top bottom 2 0 1 0 ctc ocra immediate max 3 0 1 1 fast pwm 0xff bottom max 4 1 0 0 reserved ? ? ? 5 1 0 1 pwm, phase correct ocra top bottom 6 1 1 0 reserved ? ? ? 7 1 1 1 fast pwm ocra bottom top notes: 1. max = 0xff 2. bottom = 0x00 bit 7 6 5 4 3 2 1 0 0x25 (0x45) foc0a foc0b ? ? wgm02 cs02 cs01 cs00 tccr0b read/write w w r r r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 88 ? bit 3 ? wgm02: waveform generation mode see the description in the section 15.9.1 ?tccr0a ? timer/counter control register a? on page 85 . ? bits 2:0 ? cs02:0: clock select the three clock se lect bits select the clock source to be used by the timer/counter. if external pin modes are used for the timer/counter0, transit ions on the t0 pin will clock the counter even if the pin is configured as an output. this feature allows software control of the counting. 15.9.3 tcnt0 ? timer/counter register the timer/counter register gives direct a ccess, both for read and write operations, to the timer/counter unit 8-bit counter. writing to the tcnt0 register blocks (re moves) the compare match on the followin g timer clock. modifying the counter (tcnt0) while the counter is running, introduces a risk of missing a compare match between tcnt0 and the ocr0x registers. 15.9.4 ocr0a ? output compare register a the output compare register a contains an 8-bit value that is continuou sly compared with the counter value (tcnt0). a match can be used to generate an output compare interrup t, or to generate a waveform output on the oc0a pin. 15.9.5 ocr0b ? output compare register b the output compare register b contains an 8-bit value that is continuou sly compared with the counter value (tcnt0). a match can be used to generate an output compare interrup t, or to generate a waveform output on the oc0b pin. table 15-9. clock select bit description cs02 cs01 cs00 description 0 0 0 no clock source (timer/counter stopped) 0 0 1 clk i/o /(no prescaling) 0 1 0 clk i/o /8 (from prescaler) 0 1 1 clk i/o /64 (from prescaler) 1 0 0 clk i/o /256 (from prescaler) 1 0 1 clk i/o /1024 (from prescaler) 1 1 0 external clock source on t0 pin. clock on falling edge. 1 1 1 external clock source on t0 pin. clock on rising edge. bit 76543210 0x26 (0x46) tcnt0[7:0] tcnt0 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 0x27 (0x47) ocr0a[7:0] ocr0a read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 0x28 (0x48) ocr0b[7:0] ocr0b read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 89 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 15.9.6 timsk0 ? timer/counter interrupt mask register ? bits 7:3 ? reserved these bits are reserved and will always read as zero. ? bit 2 ? ocie0b: timer/counter outp ut compare match b interrupt enable when the ocie0b bit is written to one, and the i-bit in the status r egister is set, the timer/c ounter compare match b interrupt is enabled. the corresponding interrupt is executed if a compare match in timer/co unter occurs, i.e., when the ocf0b bit is set in the timer/counter interrupt flag register ? tifr0. ? bit 1 ? ocie0a: timer/counter0 outp ut compare match a interrupt enable when the ocie0a bit is written to one, and the i-bit in the status register is set, the timer/counter0 compare match a interrupt is enabled. the corresponding interrupt is executed if a compare match in timer/coun ter0 occurs, i.e., when the ocf0a bit is set in the timer/counter 0 interrupt flag register ? tifr0. ? bit 0 ? toie0: timer/counter0 overflow interrupt enable when the toie0 bit is written to one, an d the i-bit in the status register is se t, the timer/counter0 overflow interrupt is enabled. the corresponding interrupt is exec uted if an overflow in timer/counter0 oc curs, i.e., when the tov0 bit is set in the timer/counter 0 interrupt flag register ? tifr0. 15.9.7 tifr0 ? timer/counter 0 interrupt flag register ? bits 7:3 ? reserved these bits are reserved and will always read as zero. ? bit 2 ? ocf0b: timer/counter 0 output compare b match flag the ocf0b bit is set when a compare match occurs between the timer/counter and the dat a in ocr0b ? output compare register0 b. ocf0b is cleared by hardw are when executing the corresponding interrupt handling vector. alternatively, ocf0b is cleared by writing a logic one to the flag. when the i-bit in sreg, ocie0b (t imer/counter compare b match interrupt enable), and ocf0b are set, the timer/counter compare match interrupt is executed. ? bit 1 ? ocf0a: timer/counter 0 output compare a match flag the ocf0a bit is set when a compare match occurs between th e timer/counter0 and the data in ocr0a ? output compare register0. ocf0a is cleared by hardware when executing the corresponding interrupt handling vector. alternatively, ocf0a is cleared by writing a logic one to t he flag. when the i-bit in sreg, ocie0a (timer/counter0 compare match interrupt enable), and ocf0a are set, the timer/counter0 compare match interrupt is executed. ? bit 0 ? tov0: timer/counter0 overflow flag the bit tov0 is set when an overflow occurs in timer/co unter0. tov0 is cleared by hardware when executing the corresponding interrupt handling vector. al ternatively, tov0 is cleared by writ ing a logic one to the flag. when the sreg i-bit, toie0 (timer/counter0 overfl ow interrupt enable), and tov0 are set, the timer/counter0 overflow interrupt is executed. the setting of this flag is dependent of the wgm02:0 bit setting. refer to table 15-8 on page 87 , section 15-8 ?waveform generation mode bit description? on page 87 . bit 76543 210 (0x6e) ? ? ? ? ? ocie0b ocie0a toie0 timsk0 read/write rrrrrr/wr/wr/w initial value00000 000 bit 76543210 0x15 (0x35) ? ? ? ? ?ocf0bocf0a tov0 tifr0 read/write rrrrrr/wr/wr/w initial value00000000 atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 90 16. 16-bit timer/counter1 and timer/counter3 with pwm 16.1 features true 16-bit design (i.e., allows 16-bit pwm) two independent output compare units double buffered out put compare registers one input capture unit input capture noise canceler clear timer on compare match (auto reload) glitch-free, phase correct pulse width modulator (pwm) variable pwm period frequency generator external event counter four independent interrupt sources (tov1, ocf1a, ocf1b, and icf1) 16.2 overview the 16-bit timer/counter unit allows a ccurate program execution timing (event management), wave generation, and signal timing measurement. most register and bit references in this section are written in general form. a lower case ?n? replaces the timer/counter number, and a lower case ?x? replaces the output compare unit channel. however, when us ing the register or bit defines in a program, the precise form must be us ed, i.e., tcnt1 for accessing timer/ counter1 counter value and so on. a simplified block diagram of the 16-bit timer/counter is shown in figure 16-1 on page 91 . for the actual placement of i/o pins, see section 1. ?pin configurations? on page 3 . cpu accessible i/o regist ers, including i/o bits and i/o pins, are shown in bold. the device-specific i/o regist er and bit locations are listed in the section 16.11 ?register description? on page 109 . the prtim1 bit in section 10.12.3 ?prr0 ? power reduc tion register 0? on page 39 must be written to zero to enable timer/counter1 module. 91 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 figure 16-1. 16-bit timer/counter block diagram (1) note: 1. refer to figure 1-1 on page 3 and section 14.3 ?alternate port functions? on page 62 for timer/counter1 pin placement and description. 16.2.1 registers the timer/counter (tcntn), output compare registers (o crna/b/c), and input capture register (icrn) are all 16-bit registers. special proced ures must be followed when accessing the 16-b it registers. these procedures are described in the section section 16.3 ?accessing 16-bit registers? on page 92 . the timer/counter control registers (tccrna/b/c) are 8-bit registers and have no cpu access restrictions. interrupt re quests (abbreviated to int.req. in the figure) signals are all visible in the timer interrupt flag regist er (tifrn). all interrupts are individually masked with the timer interrupt mask regi ster (timskn). tifrn and timskn are not shown in the figure. the timer/counter can be clocked internally, via the prescaler, or by an external clock source on the tn pin. th e clock select logic block controls which clock source and edge the timer/ counter uses to increment (o r decrement) its value. the timer/counter is inactive when no clock source is selected. the out put from the clock select logic is referred to as the timer clock (clktn). control logic tcntn timer/counter count clear direction clk tn ocrna ocrnb icrn tccrna tccrnb = edge detector (from prescaler) clock select top bottom tovn (int. req.) ocna (int. req.) tn waveform generation fixed top value data bus = = = 0 ocna ocnb (int. req.) waveform generation noise canceler ocnb (from analog comparator output) icfn (int. req.) edge detector icpn atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 92 the double buffered output compare registers (ocrna/b/c) are compared with the timer/counter value at all time. the result of the compare can be used by the waveform generator to generate a pwm or variable fr equency output on the output compare pin (ocna/b/c). section 16.7 ?output compare units? on page 98 . the compare match event will also set the compare match flag (ocfna/b/c) which can be used to generate an output co mpare interrupt request. the input capture register can capture the timer/counter value at a given external (edge triggered) event on either the input capture pin (icpn) or on th e analog comparator pins ( section 22. ?ac - analog comparator? on page 204 ) the input capture unit includes a digital filtering unit (noise cancele r) for reducing the chance of capturing noise spikes. the top value, or maximum timer/counter value, can in so me modes of operation be defined by either the ocrna register, the icrn register, or by a set of fixed values . when using ocrna as top value in a pwm mode, the ocrna register can not be used for ge nerating a pwm output. ho wever, the top value will in this case be double buffered allowing the top value to be changed in run time. if a fixed top value is required, the icrn register can be used as an alternative, freeing the ocrna to be used as pwm output. 16.2.2 definitions the following definitions are used extensively throughout the section: 16.3 accessing 16-bit registers the tcntn, ocrna/b/c, and icrn are 16-bit registers that can be accessed by the avr ? cpu via the 8-bit data bus. the 16-bit register must be byte accessed using two read or writ e operations. each 16-bit timer has a single 8-bit register for temporary storing of the high byte of the 16-bit access. the same te mporary register is shared between all 16-bit registers within each 16-bit timer. accessing the low byte triggers th e 16-bit read or write operatio n. when the low byte of a 16-bit register is written by th e cpu, the high byte stored in the temporary re gister, and the low byte written are both copied into the 16-bit register in the same clock cycle. when the low by te of a 16-bit register is read by the cpu, the high byte of t he 16-bit register is copied into the te mporary register in the same clo ck cycle as the low byte is read. not all 16-bit accesses uses the temporary register for th e high byte. reading the ocrna/b/ c 16-bit registers does not involve using the temporary register. to do a 16-bit write, the high byte must be written before the low byte. for a 16-bit read, the low byte must be read before th e high byte. table 16-1. definitions parameter definition bottom the counter reaches the bottom when it becomes 0x0000. max the counter reaches its max imum when it becomes 0xffff (decimal 65535). top the counter reaches the top when it becomes equal to the highest value in the count sequence. the top value can be assigned to be one of the fixed values: 0x 00ff, 0x01ff, or 0x03ff, or to the value stored in the ocrna or icrn register. the assignm ent is dependent of the mode of operation. 93 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 the following code examples show how to access the 16-bi t timer registers assuming that no interrupts updates the temporary register. the same principle can be used directly for accessing the ocrna/b/c and icrn registers. note that when using ?c?, the compiler handles the 16-bit access. note: 1. the example code assumes that t he part specific header file is included. for i/o registers located in extended i/o map, ?in?, ?out?, ?sbis?, ?sbic?, ?cbi?, and ?sbi? instructions must be replaced with instructions that allow access to extended i/o. typically ?lds? and ?sts? combined with ?sbrs?, ?sbrc?, ?sbr?, and ?cbr?. the assembly code example returns the tcntn value in the r17:r16 register pair. it is important to notice that accessing 16-bit registers are atomic operations. if an interrupt occurs between the two instructions accessing the 16-bit register , and the interrupt code updates the temp orary register by accessing the same or any other of the 16-bit timer registers, then the result of the access outside the in terrupt will be corrupted. therefore, when both the main code and the interrupt code update the temporary register, the main code must disable the interrupts during the 16-bit access. assembly code examples (1) ... ; set tcnt n to 0x01ff ldi r17,0x01 ldi r16,0xff out tcnt n h,r17 out tcnt n l,r16 ; read tcnt n into r17:r16 in r16,tcnt n l in r17,tcnt n h ... c code examples (1) unsigned int i; ... /* set tcnt n to 0x01ff */ tcnt n = 0x1ff; /* read tcnt n into i */ i = tcnt n ; ... atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 94 the following code examples show how to do an atomic read of the tcntn register contents. reading any of the ocrna/b/c or icrn registers can be done by using the same principle. note: 1. the example code assumes that t he part specific header file is included. for i/o registers located in extended i/o map, ?in?, ?out?, ?sbis?, ?sbic?, ?cbi?, and ?sbi? instructions must be replaced with instructions that allow access to extended i/o. typically ?lds? and ?sts? combined with ?sbrs?, ?sbrc?, ?sbr?, and ?cbr?. the assembly code example returns the tcntn value in the r17:r16 register pair. assembly code example (1) tim16_readtcnt n : ; save global interrupt flag in r18,sreg ; disable interrupts cli ; read tcnt n into r17:r16 in r16,tcnt n l in r17,tcnt n h ; restore global interrupt flag out sreg,r18 ret c code example (1) unsigned int tim16_readtcnt n ( void ) { unsigned char sreg; unsigned int i; /* save global interrupt flag */ sreg = sreg; /* disable interrupts */ _cli(); /* read tcnt n into i */ i = tcnt n ; /* restore global interrupt flag */ sreg = sreg; return i; } 95 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 the following code examples show how to do an atomic write of the tcntn register contents. wr iting any of the ocrna/b/c or icrn registers can be done by using the same principle. note: 1. the example code assumes that t he part specific header file is included. for i/o registers located in extended i/o map, ?in?, ?out?, ?sbis?, ?sbic?, ?cbi?, and ?sbi? instructions must be replaced with instructions that allow access to extended i/o. typically ?lds? and ?sts? combined with ?sbrs?, ?sbrc?, ?sbr?, and ?cbr?. the assembly code example requires that the r17:r16 register pair contains the value to be written to tcntn. 16.3.1 reusing the temporary high byte register if writing to more than one 16-bit regist er where the high byte is the same for a ll registers written, then the high byte only needs to be written once. however, note that the same rule of atomic operation described pr eviously also applies in this case. 16.4 timer/counter clock sources the timer/counter can be clocked by an internal or an extern al clock source. the clock sour ce is selected by the clock select logic which is controlled by th e clock select (csn2:0) bits located in the timer/counter control register b (tccrnb). for details on clock sources and prescaler, see section 17.10 ?timer/counter prescaler? on page 131 . assembly code example (1) tim16_writetcnt n : ; save global interrupt flag in r18,sreg ; disable interrupts cli ; set tcnt n to r17:r16 out tcnt n h,r17 out tcnt n l,r16 ; restore global interrupt flag out sreg,r18 ret c code example (1) void tim16_writetcnt n ( unsigned int i ) { unsigned char sreg; unsigned int i; /* save global interrupt flag */ sreg = sreg; /* disable interrupts */ _cli(); /* set tcnt n to i */ tcnt n = i; /* restore global interrupt flag */ sreg = sreg; } atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 96 16.5 counter unit the main part of the 16-bit timer/counter is the programmable 16-bit bi-directional counter unit. figure 16-2 on page 96 shows a block diagram of the counter and its surroundings. figure 16-2. counter unit block diagram signal description (internal signals): count increment or decrement tcntn by 1. direction select between increment and decrement. clear clear tcntn (set all bits to zero). clk tn timer/counter clock. top signalize that tcntn has reached maximum value. bottom signalize that tcntn has reached minimum value (zero). the 16-bit counter is mapped into two 8-bit i/o memory location s: counter high (tcntnh) containing the upper eight bits of the counter, and counter low (tcntnl) contai ning the lower eight bits. the tcntnh register can only be indirectly accessed by the cpu. when the cpu does an access to the tcntnh i/ o location, the cpu accesses the high byte temporary register (temp). the temporary register is updat ed with the tcntnh value when the tcntnl is read, and tcntnh is updated with the temporary register value when tcntnl is written. this allows the cpu to read or write the entire 16-bit counter value within one clock cycle via the 8-bit data bus. it is important to notice that there are special cases of writing to the tcntn register when the counter is counting that will give unpredict able results. the special cases are described in the sections where they are of importance. depending on the mode of operation used, the counter is cleared, increm ented, or decremented at each timer clock (clktn). the clktn can be generated from an external or internal clock source, selected by the clock select bits (csn2:0). when no clock source is selected (csn2:0 = 0) the timer is stopp ed. however, the tcntn value can be accessed by the cpu, independent of whether clktn is present or not. a cpu write overrides (has priority over) all counter clear or count operations. the counting sequence is determined by the setting of th e waveform generation mode bits (wgmn3:0) located in the timer/counter control regist ers a and b (tccrna and tccrnb). there are close connections between how the counter behaves (counts) and how waveforms ar e generated on the output compare out puts ocnx. for more details about advanced counting sequences and waveform generation, see section 16.9 ?modes of operation? on page 101 . the timer/counter overflow flag (tovn) is set according to t he mode of operation selected by the wgmn3:0 bits. tovn can be used for generating a cpu interrupt. bottom top tovn (int. req.) data bus (8-bit) control logic tcntnh (8-bit) tcntnh (16-bit counter) tcntnl (8-bit) temp (8-bit) clk tn clear count direction edge detector (from prescaler) clock select tn 97 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 16.6 input capture unit the timer/counter incorporates an input capture unit that can c apture external events and give them a time-stamp indicating time of occurrence. the external signal indicating an ev ent, or multiple events, can be applied via the icpn pin or alternatively, via the analog-comparator unit. the time-stamps can then be used to calculate freque ncy, duty-cycle, and other features of the signal applied. alternatively the time-stamps can be used for creating a log of the events. the input capture unit is illustrated by the block diagram shown in figure 16-3 on page 97 . the elements of the block diagram that are not directly a part of the input capture unit are gr ay shaded. the small ?n? in register and bit names indicates the timer/counter number. figure 16-3. input capture unit block diagram when a change of the logic level (an event) occurs on the input capture pin (icpn), alternativ ely on the analog comparator output (aco), and this change confirms to the setting of the edge detector, a captur e will be triggered. when a capture is triggered, the 16-bit value of the counter (tcntn) is written to the input capture register (icrn). the input capture flag (icf n) is set at the same system clock as the tcntn value is copied into icrn register. if enabled (i cien = 1), the input capture flag generates an input capture interrupt. the ic fn flag is automatically cleared when t he interrupt is execut ed. alternatively the icfn flag can be cleared by software by wr iting a logical one to its i/o bit location. reading the 16-bit value in the input capt ure register (icrn) is done by first read ing the low byte (icrnl) and then the high byte (icrnh). when the low byte is read the high byte is co pied into the high byte temporary register (temp). when the cpu reads the icrnh i/o location it will access the temp register. the icrn register can only be written when using a waveform gener ation mode that utilizes the ic rn register for defining the counter?s top value. in these cases the waveform generation mode (wgmn3:0) bits must be set before the top value can be written to the icrn register. when writ ing the icrn register the high byte must be written to the icrnh i/o location before the low byte is written to icrnl. for more information on how to access the 16-b it registers refer to section 16.3 ?accessing 16-bit registers? on page 92 . icfn (int. req.) icrnl (8-bit) icrnh (8-bit) icrn (16-bit register) temp (8-bit) tcntnl (8-bit) tcntnh (8-bit) tcntn (16-bit counter) data bus (8-bit) noise canceler analog comparator edge detector icnc acic* aco* write + - ices icpn atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 98 16.6.1 input capture trigger source the main trigger source for the input capture unit is the in put capture pin (icpn). timer/co unter1 can alternatively use the analog comparator output as trigger source for the input capture unit. the analog comparator is selected as trigger source by setting the analog comparator input capture (acic) bit in the analog comparator control and status register (acsr). be aware that changing trigger source can tr igger a capture. the input capture flag must therefor e be cleared after the change. both the input capture pin (icpn) and t he analog comparator output (aco) inputs are sampled using the same technique as for the tn pin ( figure 16-1 on page 91 ). the edge detector is also identical. howe ver, when the noise canceler is enabled, additional logic is inserted before the edge detector, which in creases the delay by four system clock cycles. note that the input of the noise canceler and edge detector is always enabled unless the timer/counter is set in a waveform generation mode that uses icrn to define top. an input capture can be triggered by softw are by controlling the port of the icpn pin. 16.6.2 noise canceler the noise canceler improves noise immunity by using a simple digital filtering scheme. the noise canceler input is monitored over four samples, and all four must be equal for changing the output that in turn is used by the edge detector. the noise canceler is enabled by setting the input capture noise canceler (icncn) bit in time r/counter control register b (tccrnb). when enabled the noise canceler introduces additional four system clock cycles of delay from a change applied to the input, to the update of the icrn register. the noise canc eler uses the system clock and is therefore not affected by the prescaler. 16.6.3 using the input capture unit the main challenge when using the input capture unit is to assign enough processor capacity for handling the incoming events. the time between two events is cr itical. if the processor has not read the ca ptured value in the icrn register before the next event occurs, the icrn will be overwritten with a new valu e. in this case the result of the capture will be incorrect. when using the input capture interrupt, the icrn register should be read as early in the interrupt handler routine as possible. even though the input capture interrupt has relatively high pr iority, the maximum interrupt response time is dependent on the maximum number of clock cycles it takes to handle any of the other interrupt requests. using the input capture unit in any mode of operation when the top value (resolution) is actively changed during operation, is not recommended. measurement of an external signal?s duty cycle requires that the trigger edge is changed after each capture. changing the edge sensing must be done as early as possible after the icrn register has been read. after a change of the edge, the input capture flag (icfn) must be cleared by software (writing a logi cal one to the i/o bit location). for measuring frequency only, the clearing of the icfn flag is not required (if an interrupt handler is used). 16.7 output compare units the 16-bit comparator continuously comp ares tcntn with the output compare register (ocrnx). if tcnt equals ocrnx the comparator signals a match. a match will set the output compare flag (ocfnx) at the next time r clock cycle. if enabled (ocienx = 1), the output compare flag generates an output compare interrupt. the ocfnx flag is automatically cleared when the interrupt is executed. alternatively the ocfnx flag can be cleared by software by writing a logical one to its i/o bit location. the waveform generator uses the match signal to generate an output according to operating mode set by the waveform generation mode (wgmn3:0) bits and compare output mode (comnx1:0) bits. the top and bottom signals are used by the waveform generator for handling the special cases of the extrem e values in some modes of operation ( section 16.9 ?modes of operation? on page 101 ). a special feature of output com pare unit a allows it to define the timer/coun ter top value (i.e., coun ter resolution). in addition to the counter resolution, the top value defines the period time for waveforms generated by the waveform generator. figure 16-4 on page 99 shows a block diagram of the output compare unit . the small ?n? in the register and bit names indicates the device number (n = n for timer/counter n), and t he ?x? indicates output compare unit (a/b/c). the elements of the block diagram that are not directly a part of the output compare unit are gray shaded. 99 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 figure 16-4. output comp are unit, block diagram the ocrnx register is double buffered wh en using any of the twelve pulse width modulation (pwm) modes. for the normal and clear timer on compare (ctc) modes of operation, the do uble buffering is disabled. the double buffering synchronizes the update of the ocrnx compare regist er to either top or bottom of t he counting sequence. the synchronization prevents the occurrence of odd-length, non-symmetrical pwm pulses, thereby maki ng the output glitch-free. the ocrnx register access may seem co mplex, but this is not case. when th e double buffering is enabled, the cpu has access to the ocrnx buffer register, and if double buffering is disabled the cpu will access th e ocrnx directly. the content of the ocr1x (buffer or compare) register is only changed by a write operation (the timer/ counter does not update this register automatically as the tcnt1 and i cr1 register). therefore ocr1x is not r ead via the high byte temporary register (temp). however, it is a good practice to read the low byte fi rst as when accessing other 16-b it registers. writing the ocrnx registers must be done via the temp register since the compare of all 16 bits is done continuously. the high byte (ocrnxh) has to be written first. when the high byte i/o location is written by the cpu, th e temp register will be updated by the value written. then when the low byte (ocrnxl) is written to the lowe r eight bits, the high byte will be copied into the upper 8-bits of either the ocrnx buffer or ocrnx compar e register in the same system clock cycle. for more information of how to access the 16-bit registers refer to section 16.3 ?accessing 16-bit registers? on page 92 . 16.7.1 force output compare in non-pwm waveform generation modes, the match output of the comparator can be forced by writing a one to the force output compare (focnx) bit. forc ing compare match will not set the ocfnx flag or reload/clear the timer, but the ocnx pin will be updated as if a real compare match had occurred (the comn1:0 bits settings define w hether the ocnx pin is set, cleared or toggled). ocrnxl buf. (8-bit) ocrnxh buf. (8-bit) ocrnx buffer (16-bit register) temp (8-bit) ocrnxl (8-bit) ocfnx (int. req.) ocrnxh (8-bit) ocrnx (16-bit register) = (16-bitcomparator) wgmn3:0 comnx1:0 waveform generator tcntnl (8-bit) tcntnh (8-bit) tcntn (16-bit counter) data bus (8-bit) ocnx top bottom atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 100 16.7.2 compare match blocking by tcntn write all cpu writes to the tcntn register will block any compare matc h that occurs in the next timer clock cycle, even when the timer is stopped. this feature allows ocrnx to be initialized to the same value as tcntn without triggering an interrupt when the timer/counter clock is enabled. 16.7.3 using the ou tput compare unit since writing tcntn in any mode of ope ration will block all compare matches for one timer clock cycle, there are risks involved when changing tcntn when using any of the output compare channels, independent of whether the timer/counter is running or not. if the value written to tcntn equals the ocrnx value, the com pare match will be missed, resulting in incorrect waveform generation. do not write the tcntn equa l to top in pwm modes with variable top values. the compare match for the top will be ignored and the counter will continue to 0xffff. si milarly, do not write the tcntn value equal to bottom when the counter is downcounting. the setup of the ocnx should be performed bef ore setting the data direction register for the port pin to output. the easiest way of setting the ocnx value is to use the force output co mpare (focnx) strobe bits in normal mode. the ocnx register keeps its value even when changing between waveform generation modes. be aware that the comnx1:0 bits are not double buffered together with the compar e value. changing the comnx1:0 bits will take effect immediately. 16.8 compare match output unit the compare output mode (comnx1:0) bits have two functi ons. the waveform generator uses the comnx1:0 bits for defining the output oompare (ocnx) state at the next compare match. secondly th e comnx1:0 bits control the ocnx pin output source. figure 16-5 shows a simplified schematic of the logic affected by the comnx1:0 bit sett ing. the i/o registers, i/o bits, and i/o pins in the figure are shown in bold. only the parts of the general i/o port control registers (ddr and port) that are affected by the comnx1:0 bits ar e shown. when referring to the ocnx state, the reference is for the internal ocnx register, not the ocnx pin. if a system rese t occur, the ocnx register is reset to ?0?. figure 16-5. compare match output unit, schematic data bus 0 1 q d comnx1 comnx0 focnx ocnx waveform generator q d port q d ddr ocnx pin clk i/o 101 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 the general i/o port function is overridden by the output co mpare (ocnx) from the waveform generator if either of the comnx1:0 bits are set. however, the ocnx pin direction (input or output) is still controlled by the data direction register (ddr) for the port pin. the data direction register bit for the ocnx pin (ddr_oc nx) must be set as output before the ocnx value is visible on the pin. the port override function is generally independent of the waveform generation mode, but there are some exceptions. refer to table 16-2 on page 109 , table 16-3 on page 110 and table 16-4 on page 110 for details. the design of the output compare pin logic allows initialization of the ocnx state before the output is enabled. note that some comnx1:0 bit settings are reserved for certain modes of operation. section 16.11 ?register description? on page 109 . the comnx1:0 bits have no effect on the input capture unit. 16.8.1 compare output mode and waveform generation the waveform generator uses the comnx1:0 bits differentl y in normal, ctc, and pwm modes. for all modes, setting the comnx1:0 = 0 tells the waveform generator that no action on the ocnx register is to be performed on the next compare match. for compare output actions in the non-pwm modes refer to table 16-2 on page 109 . for fast pwm mode refer to table 16-3 on page 110 , and for phase correct and phase and frequency correct pwm refer to table 16-4 on page 110 . a change of the comnx1:0 bits state will have effect at the first compare match after the bi ts are written. for non-pwm modes, the action can be forced to have immedi ate effect by using the focnx strobe bits. 16.9 modes of operation the mode of operation, i.e., t he behavior of the timer/counter and the output compare pins, is defined by the combination of the waveform generation mode (wgmn3:0) and compare output mode (comnx1:0) bits. the compare output mode bits do not affect the counting sequence, while t he waveform generation mode bits do. the comnx1:0 bits control whether the pwm output generated should be inverted or not (inverted or non-inverted pwm). for non-p wm modes the comnx1:0 bits control whether the output should be set, cleared or toggle at a compare match ( section 16.8 ?compare match output unit? on page 100 ). for detailed timing information refer to section 16.10 ?timer/counter timing diagrams? on page 107 . 16.9.1 normal mode the simplest mode of operation is t he normal mode (wgmn3:0 = 0). in this mo de the counting direction is always up (incrementing), and no counter clear is performed. the counte r simply overruns when it passes its maximum 16-bit value (max = 0xffff) and then restarts from th e bottom (0x0000). in normal operation the timer/counter overflow flag (tovn) will be set in the same timer clock cycle as the tcntn becomes zero. the tovn flag in this ca se behaves like a 17th bit, except that it is only set, not cleared. however, combined with the timer overflow interrupt that automatically clears the tovn flag, the timer resolution can be increased by software. there are no special cases to consider in the normal mode, a new counter value can be written anytime. the input capture unit is easy to use in normal mode. howeve r, observe that the maximum interval between the external events must not exceed the resolution of the counter. if the interval between events are too long, the timer overflow interrupt or the prescaler must be used to exte nd the resolution for the capture unit. the output compare units can be used to generate interrupts at some given ti me. using the output compare to generate waveforms in normal mode is not recommended, since this will occupy too much of the cpu time. 16.9.2 clear timer on compare match (ctc) mode in clear timer on compare or ctc mode (wgmn3:0 = 4 or 12) , the ocrna or icrn register are used to manipulate the counter resolution. in ctc mode the count er is cleared to zero when the counter value (tcntn) matches either the ocrna (wgmn3:0 = 4) or the icrn (wgmn3:0 = 12) . the ocrna or icrn define the top value for the counter, hence also its resolution. this mode allows greater control of the compare match output frequency. it also simplifies the operation of counting external events. the timing diagram for the ctc mode is shown in figure 16-6 on page 102 . the counter value (tcntn) increases until a compare match occurs with either ocrna or icrn, and then counter (tcntn) is cleared. atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 102 figure 16-6. ctc mode, timing diagram an interrupt can be generated at each time the counter value re aches the top value by either using the ocfna or icfn flag according to the register used to define the top value. if th e interrupt is enabled, the inte rrupt handler routine can be used for updating the top value. however, changing the top to a value close to bottom when the counter is running with none or a low prescaler value must be done with care since the ctc mode does not have the double buffering feature. if the new value written to ocrna or icrn is lower than the current value of tcntn, the counter will miss the compare match. the counter will then have to count to its maximum value (0xfff f) and wrap around starting at 0x0000 before the compare match can occur. in many cases this f eature is not desirable. an alternative wi ll then be to use the fast pwm mode using ocrna for defining top (wgmn3:0 = 15) since the ocrna then will be double buffered. for generating a waveform output in ctc mode, the ocna output can be set to to ggle its logical level on each compare match by setting the compare output mode bits to toggle mode (comna1:0 = 1). the ocna value will not be visible on the port pin unless the data direction for the pin is set to output (ddr_ocna = 1). the waveform generated will have a maximum frequency of f ocna = f clk_i/o /2 when ocrna is set to zero (0x0000). the waveform frequency is defined by the following equation: the n variable represents the prescaler fa ctor (1, 8, 64, 256, or 1024). as for the normal mode of opera tion, the tovn flag is set in the same timer clock cycle that the counter counts from max to 0x0000. 16.9.3 fast pwm mode the fast pulse width modulation or fast pwm mode (wgmn3:0 = 5, 6, 7, 14, or 15) provides a high frequency pwm waveform generation option. the fast pwm differs from the other pwm options by its single-slope operation. the counter counts from bottom to top then restarts from bottom. in non-inverting compare output mode, the output compare (ocnx) is cleared on the compare match between tcntn and ocrnx, and set at bottom. in inverting compare output mode output is set on compare match a nd cleared at bottom. due to the single -slope operation, the operating frequency of the fast pwm mode can be twice as high as the phase correct and phase and frequency correct pwm modes that use dual-slope operation. this high frequency makes the fast pwm mode well suited for power regula tion, rectification, and dac applications. high frequency allows physically small sized ex ternal components (coils, capacitors), hence reduces total system cost. the pwm resolution for fast pwm can be fixed to 8-, 9-, or 10-bit, or defined by either icrn or ocrna. the minimum resolution allowed is 2-bit (icrn or ocrna set to 0x0003), and the maximum resolution is 16-bit (icrn or ocrna set to max). the pwm resolution in bits can be calculated by using the following equation: 12 tcntn (comna1:0 = 1) ocna (toggle) period 3 ocna interrupt flag set or icfn interrupt flag set (interrupt on top) 4 f ocna f clk_i/o 2 n 1 ocrna + () ?? ------------------------------------------------- - = r fpwm top 1 + () log 2 () log ---------------------------------- = 103 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 in fast pwm mode the counter is incremented until the count er value matches either one of the fixed values 0x00ff, 0x01ff, or 0x03ff (wgmn3:0 = 5, 6, or 7), the value in icrn (wgmn3:0 = 14), or the value in ocrna (wgmn3:0 = 15). the counter is then cleared at the following timer clock cy cle. the timing diagram for the fast pwm mode is shown in figure 16-7 . the figure shows fast pwm mode when ocrna or icrn is used to define top. the tcntn value is in the timing diagram shown as a histogram for illustrating the single-slope operation. the diagram includes non-inverted and inverted pwm outputs. the sm all horizontal line marks on the tcntn slopes represent compare matches between ocrnx and tcntn. the ocnx interr upt flag will be set when a compare match occurs. figure 16-7. fast pwm mode, timing diagram the timer/counter overflow flag (tovn) is set each time the coun ter reaches top. in addition the ocna or icfn flag is set at the same timer clock cycle as tovn is set when either ocrna or icrn is used for defining the to p value. if one of the interrupts are enabled, the interrupt handler routine can be used for updating the top and compare values. when changing the top value the program must ensure that the new top value is higher or equal to the value of all of the compare registers. if the top value is lower than any of the compare registers, a compare match will never occur between the tcntn and the ocrnx. note that when using fixed top valu es the unused bits are masked to zero when any of the ocrnx registers are written. the procedure for updating icrn differs from updating ocrna wh en used for defining the top value. the icrn register is not double buffered. this means that if icrn is changed to a low value when the counter is running with none or a low prescaler value, there is a risk that the new icrn value written is lower than the cu rrent value of tcntn. the result will then be that the counter will miss the compare match at the top val ue. the counter will then have to count to the max value (0xffff) and wrap around starting at 0x0000 before the comp are match can occur. the ocrna register however, is double buffered. this feature allows the ocrna i/o location to be written anytime. w hen the ocrna i/o location is written the value written will be put into the ocrna buffer register. the ocrna compare register will then be updated with the value in the buffer register at the next timer clock cycle the tcntn matches top. the upd ate is done at the same timer clock cycle as the tcntn is cleared and the tovn flag is set. using the icrn register for defining top works well when using fixed top values. by using icrn, the ocrna register is free to be used for generating a pwm output on ocna. ho wever, if the base pwm frequency is actively changed (by changing the top value), using the ocrna as top is clearly a better choice due to its double buffer feature. 12345 tcntn (comnx1:0 = 2) ocnx ocnx period ocrnx/ top update and tovn interrupt flag set and ocna interrupt flag set or icfn interrupt flag set (interrupt on top) 67 8 (comnx1:0 = 3) atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 104 in fast pwm mode, the compare units allow generation of pwm waveforms on the ocnx pins. setting the comnx1:0 bits to two will produce a non-inverted pwm and an inverted pwm output can be generated by setting the comnx1:0 to three (see table on page 110 ). the actual ocnx value will only be visible on the po rt pin if the data direction for the port pin is set as output (ddr_ocnx). the pwm waveform is generated by setting (or clearing) the ocnx register at the compare match between ocrnx and tcntn, and cl earing (or setting) the ocnx register at the timer cloc k cycle the counter is cleared (changes from top to bottom). the pwm frequency for the output can be calculated by the following equation: the n variable represents the prescaler divider (1, 8, 64, 256, or 1024). the extreme values for the ocrnx register represents special cases when generating a pwm waveform output in the fast pwm mode. if the ocrnx is set equal to bottom (0x0000) t he output will be a narrow spike for each top+1 timer clock cycle. setting the ocrnx equal to top will re sult in a constant high or low output (depending on the polarity of the output set by the comnx1:0 bits.) a frequency (with 50% duty cycle) waveform ou tput in fast pwm mode ca n be achieved by setting ocna to toggle its logical level on each compare match (comna1:0 = 1). this applies only if ocr1a is used to define the top value (wgm13:0 = 15). the waveform generated will have a maximum frequency of f ocna = f clk_i/o /2 when ocrna is set to zero (0x0000). this feature is similar to the ocna toggle in ctc mode, except the double buffer feature of the output compare unit is enabled in the fast pwm mode. 16.9.4 phase correct pwm mode the phase correct pulse width modulation or phase correct pw m mode (wgmn3:0 = 1, 2, 3, 10, or 11) provides a high resolution phase correct pwm waveform generation option. the phase correct pwm mode is, like the phase and frequency correct pwm mode, based on a dual-slope operation. the coun ter counts repeatedly from bo ttom (0x0000) to top and then from top to bottom. in non-inverting compare output m ode, the output compare (ocnx) is cleared on the compare match between tcntn and ocrnx while upcounting, and set on the compare match while downcoun ting. in inverting output compare mode, the operation is inverted . the dual-slope operation has lower maximum operation frequency than single slope operation. however, due to the symme tric feature of the dual-slope pwm mode s, these modes are preferred for motor control applications. the pwm resolution for the phase correct pwm mode can be fixed to 8-, 9-, or 10-bit, or defined by either icrn or ocrna. the minimum resolution allowed is 2-bit (icrn or ocrna set to 0x0003), and the maximum resolution is 16-bit (icrn or ocrna set to max). the pwm resolution in bits can be calculated by using the following equation: in phase correct pwm mode the counter is incremented until the counter value matches either one of the fixed values 0x00ff, 0x01ff, or 0x03ff (wgmn3:0 = 1, 2, or 3), the value in icrn (wgmn3:0 = 10), or the value in ocrna (wgmn3:0 = 11). the counter has then reached the top and changes the count direction. the tcntn value will be equal to top for one timer clock cycle. the timing diagram for the phase correct pwm mode is shown on figure 16-8 on page 105 . the figure shows phase correct pwm mode when ocrna or icrn is used to define top. the tcntn value is in the timing diagram shown as a histogram for illustrating the dual-slo pe operation. the diagram includes non-inverted and inverted pwm outputs. the small horizontal line marks on the t cntn slopes represent compare matches between ocrnx and tcntn. the ocnx interrupt flag will be set when a compare match occurs. f ocnxpwm f clk_i/o n 1 top + () ? ---------------------------------- = r pcpwm top 1 + () log 2 () log ---------------------------------- = 105 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 figure 16-8. phase correct pwm mode, timing diagram the timer/counter overflow flag (tovn) is set each time th e counter reaches bottom. when either ocrna or icrn is used for defining the top va lue, the ocna or icfn flag is set accord ingly at the same timer clock cycle as the ocrnx registers are updated with the double buffer value (at top). the interrupt flags can be used to generate an interrupt each time the counter reaches the top or bottom value. when changing the top value the program must ensure that the new top value is higher or equal to the value of all of the compare registers. if the top value is lower than any of the compare registers, a compare match will never occur between the tcntn and the ocrnx. note that when using fixed top va lues, the unused bits are masked to zero when any of the ocrnx registers are written. as the third period shown in figure 16-8 illustrates, changing the top actively while the timer/counter is running in the phase correct mode can result in an unsymmetrical output. the reason for this can be found in the time of update of the ocrnx register. since the ocrnx update occurs at top, the pwm period starts and ends at top. this implies that the length of t he falling slope is determined by the previous top value, while t he length of the rising slope is determined by the new top value. when these two values differ the two slopes of the period will differ in length. the difference in length gives the unsy mmetrical result on the output. it is recommended to use the phase and frequency correct mode instead of the phase correct mode when changing the top value while the timer/counter is running. when using a static top value there ar e practically no differences between the two modes of operation. in phase correct pwm mode, the compare units allow gener ation of pwm waveforms on t he ocnx pins. setting the comnx1:0 bits to two will produce a non-inverted pwm and an inverted pwm output can be generated by setting the comnx1:0 to three (see table on page 110 ). the actual ocnx value will only be visible on the port pin if the data direction for the port pin is set as output (ddr_oc nx). the pwm waveform is gen erated by setting (or clearing) the ocnx register at the compare match between ocrnx and tcntn when the counter incr ements, and clearing (or setting) the ocnx register at compare match between ocrnx and tcntn when the counter decrements. the pwm frequency for the output when using phase correct pwm can be calculated by the following equation: the n variable represents the prescaler divider (1, 8, 64, 256, or 1024). the extreme values for the ocrnx regist er represent special cases when generatin g a pwm waveform output in the phase correct pwm mode. if the ocrnx is set equal to bottom the out put will be continuously low and if set equal to top the output will be continuously high for no n-inverted pwm mode. for inverted pwm the output will have the opposite logic values. if ocr1a is used to define the top value (wgm13:0 = 11) and com1a1:0 = 1, the oc1a output will toggle with a 50% duty cycle. 1 2 34 tcntn (comnx1:0 = 2) (comnx1:0 = 3) ocnx ocnx period tovn interrupt flag set (interrupt on bottom) ocrnx/ top update and ocna interrupt flag set or icfn interrupt flag set (interrupt on top) f ocnxpcpwm f clk_i/o 2 ntop ?? --------------------------- - = atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 106 16.9.5 phase and frequency correct pwm mode the phase and frequency correct pulse width modulation, or phase and frequency correct pwm mode (wgmn3:0 = 8 or 9) provides a high resolution phase and frequency correct pwm waveform generation option. the phase and frequency correct pwm mode is, like the phase correct pwm mode, based on a dual-slope operation. the counter counts repeatedly from bottom (0x0000) to top and then from top to bottom. in non-inverting compare outpu t mode, the output compare (ocnx) is cleared on the compare match between tcntn and ocrnx while upcounting, and set on the compare match while downcounting. in inverting compare output mode, the ope ration is inverted. the dual-slope operation gives a lower maximum operation frequency compared to the single-slope operation. however, due to t he symmetric feature of the dual-slope pwm modes, these modes are pr eferred for motor control applications. the main difference between the phase correct, and the ph ase and frequency correct pwm mode is the time the ocrnx register is updated by the oc rnx buffer register, (see figure 16-8 on page 105 and figure 16-9 ). the pwm resolution for the phase and frequency correct pw m mode can be defined by either icrn or ocrna. the minimum resolution allowed is 2-bit (icrn or ocrna set to 0x0003), and the maximum resolution is 16-bit (icrn or ocrna set to max). the pwm resolution in bits can be calculated using the following equation: in phase and frequency correct pwm mode the counter is incr emented until the counter value matches either the value in icrn (wgmn3:0 = 8), or the value in ocrna (wgmn3:0 = 9). the counter has then reached the top and changes the count direction. the tcntn value will be equal to top for o ne timer clock cycle. the timing diagram for the phase correct and frequency correct pwm mode is shown on figure 16-9 . the figure shows phase and frequency correct pwm mode when ocrna or icrn is used to define top. the tcntn value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. the diagram includes non-inverted a nd inverted pwm outputs. the small horizontal line marks on the tcntn slopes represent compare ma tches between ocrnx and tcntn. the ocnx interrupt flag will be set when a compare match occurs. figure 16-9. phase and frequency correct pwm mode, timing diagram the timer/counter overflow fl ag (tovn) is set at the same timer clock cycl e as the ocrnx regist ers are updat ed with the double buffer value (at bottom). when either ocrna or icrn is used for defining the top value, the ocna or icfn flag set when tcntn has reached top. the interrupt flags can then be used to generate an interrupt each time the counter reaches the top or bottom value. when changing the top value the program must ensure that the new top value is higher or equal to the value of all of the compare registers. if the top value is lower than any of the compare registers, a compare match will never occur between the tcntn and the ocrnx. r pfcpwm top 1 + () log 2 () log ---------------------------------- = 1 2 34 tcntn (comnx1:0 = 2) (comnx1:0 = 3) ocnx ocnx period ocna interrupt flag set or icfn interrupt flag set (interrupt on top) ocrnx/ top update and tovn interrupt flag set (interrupt on bottom) 107 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 as figure 16-9 on page 106 shows the output generated is, in contrast to the phase correct mode, symmetrical in all periods. since the ocrnx registers are updated at bottom, the length of the rising and the falling slopes will always be equal. this gives symmetrical output pulses and is therefore frequency correct. using the icrn register for defining top works well when using fixed top values. by using icrn, the ocrna register is free to be used for generating a pwm output on ocna. ho wever, if the base pwm frequency is actively changed by changing the top value, using the ocrna as top is clearly a better choice due to its double buffer feature. in phase and frequency correct pwm mode, the compare unit s allow generation of pwm waveforms on the ocnx pins. setting the comnx1:0 bits to two will produce a non-inverted pwm and an inverted pwm output can be generated by setting the comnx1:0 to three (see table on page 110 ). the actual ocnx value will only be visible on the port pin if the data direction for the port pin is set as output (ddr_ocnx). the pwm waveform is generated by setting (or clearing) the ocnx register at the compare match between oc rnx and tcntn when the counter increment s, and clearing (or setting) the ocnx register at compare match be tween ocrnx and tcntn when the counter decr ements. the pwm frequency for the output when using phase and frequency correct pwm can be calculated by the following equation: the n variable represents the prescaler divider (1, 8, 64, 256, or 1024). the extreme values for the ocrnx register represents spec ial cases when generating a pwm waveform output in the phase correct pwm mode. if the ocrnx is set equal to bottom the out put will be continuously low and if set equal to top the output will be set to high for non-inverted pwm mode. for inve rted pwm the output will have the opposite logic values. if ocr1a is used to define the top value (wgm13:0 = 9) and co m1a1:0 = 1, the oc1a output will toggle with a 50% duty cycle. 16.10 timer/counter timing diagrams the timer/counter is a synchronous design and the timer clock (clk tn ) is therefore shown as a clock enable signal in the following figures. the figures include information on when interr upt flags are set, and when t he ocrnx register is updated with the ocrnx buffer value (only fo r modes utilizing double buffering). figure 16-10 shows a timing diagram for the setting of ocfnx. figure 16-10. timer/counter timing diagram, setting of ocfnx, no prescaling f ocnxpfcpwm f clk_i/o 2 ntop ?? --------------------------- - = ocrnx - 1 clk i/o (clk i/o /1) tcntn ocrnx ocfnx clk tn ocrnx ocrnx value ocrnx + 1 ocrnx + 2 atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 108 figure 16-11 shows the same timing data, but with the prescaler enabled. figure 16-11. timer/counter timing diagra m, setting of ocfnx, with prescaler (f clk_i/o /8) figure 16-12 shows the count sequence close to top in various modes. when using phase and frequency correct pwm mode the ocrnx register is updated at bottom. the timing diagrams will be the sa me, but top should be replaced by bottom, top-1 by bottom+1 and so on. the same renamin g applies for modes that set the tovn flag at bottom. figure 16-12. timer/counter ti ming diagram, no prescaling ocrnx - 1 clk i/o (clk i/o /8) tcntn ocrnx ocfnx clk tn ocrnx ocrnx + 1 ocrnx value ocrnx + 2 top - 1 clk i/o (clk i/o /1) tcntn (ctc and fpwm) ocrnx (update at top) tcntn (pc and pfc pwm) tovn (fpwm) and icfn (if used as top) clk tn top old ocrnx value new ocrnx value bottom bottom + 1 top - 1 top top -1 top -2 109 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 figure 16-13 shows the same timing data, but with the prescaler enabled. figure 16-13. timer/counter timi ng diagram, with prescaler (f clk_i/o /8) 16.11 register description 16.11.1 tccrna ? timer/counte r n control register a ? bit 7:6 ? comna1:0: compare output mode for channel a ? bit 5:4 ? comnb1:0: compare output mode for channel b the comna1:0 and comnb1:0 control the output compare pins (ocna and ocnb respectively) behavior. if one or both of the comna1:0 bits are written to one, the ocna output overri des the normal port functionality of the i/o pin it is connected to. if one or both of the comnb1:0 bit are written to one, the ocnb output overrides the normal port functionality of the i/o pin it is connected to. however, note that the data direction register (ddr) bit corresponding to the ocna or ocnb pin must be set in order to enable the output driver. when the ocna or ocnb is connected to the pin, the functi on of the comnx1:0 bits is dependent of the wgmn3:0 bits setting. table 16-2 shows the comnx1:0 bit functionality when the wg mn3:0 bits are set to a normal or a ctc mode (non-pwm). top - 1 top bottom bottom + 1 top - 1 top top - 1 top - 2 clk i/o (clk i/o /8) tcntn (ctc and fpwm) ocrnx (update at top) tcntn (pc and pfc pwm) tovn (fpwm) and icfn (if used as top) clk tn old ocrnx value new ocrnx value bit 7 6 5 4 3210 (0x80) comna1 comna0 comnb1 comnb0 ? ? wgmn1 wgmn0 tccrna read/write r/w r/w r/w r/w r r r/w r/w initial value0 0 0 0 0000 table 16-2. compare output mode, non-pwm comna1/comnb1 comna0/comnb0 description 0 0 normal port operation, ocna/ocnb disconnected. 0 1 toggle ocna/ocnb on compare match. 1 0 clear ocna/ocnb on compare match (set output to low level) 1 1 set ocna/ocnb on compare match (set output to high level) atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 110 table 16-3 shows the comnx1:0 bit functionality when th e wgmn3:0 bits are set to the fast pwm mode. table 16-4 shows the comnx1:0 bit functionality when the wgmn3: 0 bits are set to the phase correct or the phase and frequency correct, pwm mode. ? bit 1:0 ? wgmn1:0: wa veform gene ration mode combined with the wgmn3:2 bits found in the tccrnb register, t hese bits control the counting sequence of the counter, the source for maximum (top) counter value, and w hat type of waveform generation to be used, see table 16-5 . modes of operation supported by the timer/counter unit are: normal mode (counter), clear timer on compare match (ctc) mode, and three types of pulse width modulation (pwm) modes. see ( section 16.9 ?modes of operation? on page 101 ). table 16-3. compare output mode, fast pwm (1) comna1/comnb1 comna0/comnb0 description 0 0 normal port operation, ocna/ocnb disconnected. 0 1 wgmn3:0 = 14 or 15: toggle oc1a on compare match, oc1b disconnected (normal port oper ation). for all other wgm1 settings, normal port operation, oc1a/oc1b disconnected. 1 0 clear ocna/ocnb on compare match, set ocna/ocnb at bottom (non-inverting mode) 1 1 set ocna/ocnb on compare match, clear ocna/ocnb at bottom (inverting mode) note: 1. a special case occurs when ocrna/ocrnb equals top and comna1/comnb1 is set. in this case the compare match is ignored, but the set or clear is done at bottom. see section 16.9.3 ?fast pw m mode? on page 102 for more details. table 16-4. compare output mode, phase correct and phase and frequency correct pwm (1) comna1/comnb1 comna0/comnb0 description 0 0 normal port operation, ocna/ocnb disconnected. 0 1 wgmn3:0 = 9 or 11: toggle ocna on compare match, ocnb disconnected (normal port operation). for all other wgm1 settings, normal port operation, oc1a/oc1b disconnected. 1 0 clear ocna/ocnb on compare match when up-counting. set ocna/ocnb on compare match when downcounting. 1 1 set ocna/ocnb on compare match when up-counting. clear ocna/ocnb on compare match when downcounting. note: 1. a special case occurs when ocrna/ocrnb equals top and comna1/comnb1 is set. see section 16.9.4 ?phase correct pwm mode? on page 104 for more details. 111 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 16.11.2 tccrnb ? timer/counte r n control register b ? bit 7 ? icncn: input capture noise canceler setting this bit (to one) activates the input capture noise cancel er. when the noise canceler is activated, the input from the input capture pin (icpn) is filtered. the filter function requires four successive equal valued samples of the icpn pin for changing its output. the input capture is therefore delayed by four oscillator cycles when the noise canceler is enabled. ? bit 6 ? icesn: input capture edge select this bit selects which edge on the input capture pin (icpn) t hat is used to trigger a capture event. when the icesn bit is written to zero, a falling (negative) edge is used as trigger, and when the icesn bit is written to one, a rising (positive) ed ge will trigger the capture. when a capture is triggered according to the icesn setting, the counter value is copied into the input capture register (icrn). the event will also set the input ca pture flag (icfn), and this can be used to cause an input capture interrupt, if thi s interrupt is enabled. when the icrn is used as top value (see description of the wgmn3:0 bits located in the tccrna and the tccrnb register), the icpn is disconnected and consequ ently the input capture function is disabled. ? bit 5 ? reserved this bit is reserved for future use. for ensuring compatibilit y with future devices, this bit must be written to zero when tccrnb is written. table 16-5. waveform generation mode bit description (1) mode wgmn3 wgmn2 (ctcn) wgmn1 (pwmn1) wgmn0 (pwmn0) timer/counter mode of operation top update of ocrn x at tovn flag set on 0 0 0 0 0 normal 0xffff immediate max 1 0 0 0 1 pwm, phase correct, 8-bit 0x00ff top bottom 2 0 0 1 0 pwm, phase correct, 9-bit 0x01ff top bottom 3 0 0 1 1 pwm, phase correct, 10-bit 0x03ff top bottom 4 0 1 0 0 ctc ocrna immediate max 5 0 1 0 1 fast pwm, 8-bit 0x00ff bottom top 6 0 1 1 0 fast pwm, 9-bit 0x01ff bottom top 7 0 1 1 1 fast pwm, 10-bit 0x03ff bottom top 8 1 0 0 0 pwm, phase and frequency correct icrn bottom bottom 9 1 0 0 1 pwm, phase and frequency correct ocrna bottom bottom 10 1 0 1 0 pwm, phase correct icrn top bottom 11 1 0 1 1 pwm, phase correct ocrna top bottom 12 1 1 0 0 ctc icrn immediate max 13 1 1 0 1 (reserved) ? ? ? 14 1 1 1 0 fast pwm icrn bottom top 15 1 1 1 1 fast pwm ocrna bottom top note: 1. the ctcn and pwmn1:0 bit definition names are obsolete. use the wgm n2:0 definitions. however, the functionality and location of these bits are co mpatible with previous versions of the timer. bit 7654 3210 (0x81) icncn icesn ? wgmn3 wgmn2 csn2 csn1 csn0 tccrnb read/write r/w r/w r r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 112 ? bit 4:3 ? wgmn3:2: wa veform gene ration mode see description of section 16.11.1 ?tccrna ? timer/count er n control register a? on page 109 . ? bit 2:0 ? csn2:0: clock select the three clock sele ct bits select the clock source to be used by the timer/counter, see figure 16-10 on page 107 and figure 16-11 on page 108 . if external pin modes are used for the timer/countern, transit ions on the tn pin will clock the counter even if the pin is configured as an output. this feature allows software control of the counting. 16.11.3 tccrnc ? timer/counte r n control register c ? bit 7 ? focna: force output compare for channel a ? bit 6 ? focnb: force output compare for channel b the focna/focnb bits are only active when the wgmn3:0 bits specifies a non-pwm mode. however, for ensuring compatibility with future devices, these bits must be set to zero when tccrna is written when operating in a pwm mode. when writing a logical one to the focna/focnb bit, an imm ediate compare match is forced on the waveform generation unit. the ocna/ocnb output is changed according to its comn x1:0 bits setting. note that the focna/focnb bits are implemented as strobes. therefore it is the value present in the comnx1:0 bits that dete rmine the effect of the forced compare. a focna/focnb strobe will not generate any interrupt nor will it clear the timer in clear timer on compare match (ctc) mode using ocrna as top. the focna/focnb bits are always read as zero. table 16-6. clock select bit description csn2 csn1 csn0 description 0 0 0 no clock source (timer/counter stopped). 0 0 1 clk i/o /1 (no prescaling) 0 1 0 clk i/o /8 (from prescaler) 0 1 1 clk i/o /64 (from prescaler) 1 0 0 clk i/o /256 (from prescaler) 1 0 1 clk i/o /1024 (from prescaler) 1 1 0 external clock source on tn pin. clock on falling edge. 1 1 1 external clock source on tn pin. clock on rising edge. bit 7654 3210 (0x82) focna focnb ? ? ? ? ? ? tccrnc read/write r/w r/w r r r r r r initial value 0 0 0 0 0 0 0 0 113 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 16.11.4 tcnt1h and tcnt1l ?timer/counter1 the two timer/counter i/o locations (tcnt1h and tcnt1l, combined tcnt1) give direct access, both for read and for write operations, to the timer/counter unit 16-bit counter. to ensure that both th e high and low bytes are read and written simultaneously when the cpu accesses thes e registers, the access is performed usi ng an 8-bit temporary high byte register (temp). this temporary register is shar ed by all the other 16-bit registers. see section 16.3 ?accessing 16-bit registers? on page 92 . modifying the counter (tcnt1) while the counter is running introduces a risk of missing a compare match between tcnt1 and one of the ocrnx registers. writing to the tcnt1 register blocks (removes) the compare match on the follo wing timer clock for all compare units. 16.11.5 tcnt3h and tcnt3l ?timer/counter3 the two timer/counter i/o locations (tcnt3h and tcnt3l, combined tcnt3) give direct access, both for read and for write operations, to the timer/counter unit 16-bit counter. to ensure that both th e high and low bytes are read and written simultaneously when the cpu accesses thes e registers, the access is performed usi ng an 8-bit temporary high byte register (temp). this temporary register is shar ed by all the other 16-bit registers. see section 16.3 ?accessing 16-bit registers? on page 92 . modifying the counter (tcnt3) while the counter is running introduces a risk of missing a compare match between tcnt3 and one of the ocrnx registers. writing to the tcnt3 register blocks (removes) the compare match on the follo wing timer clock for all compare units. 16.11.6 ocr1ah and ocr1al ? output compare register1 a bit 76543210 (0x85) tcnt1[15:8] tcnt1h (0x84) tcnt1[7:0] tcnt1l read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 (0x95) tcnt3[15:8] tcnt3h (0x94) tcnt3[7:0] tcnt3l read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 (0x89) ocr1a[15:8] ocr1ah (0x88) ocr1a[7:0] ocr1al read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 114 16.11.7 ocr1bh and ocr1bl ? output compare register1 b the output compare registers contain a 16 -bit value that is continuously compar ed with the counter value (tcnt1). a match can be used to generate an output compare interrupt, or to generate a waveform output on the ocnx pin. the output compare registers are 16-bit in size. to ensure that both the high and low bytes are written simultaneously when the cpu writes to these registers, the access is performed using an 8-bit temporary high byte register (temp). this temporary register is shared by al l the other 16-bit registers. see section 16.3 ?accessing 16-bit registers? on page 92 . 16.11.8 ocr3ah and ocr3al ? output compare register3 a 16.11.9 ocr3bh and ocr3bl ? output compare register3 b the output compare registers contain a 16 -bit value that is continuously compar ed with the counter value (tcnt3). a match can be used to generate an output compare interrupt, or to generate a waveform output on the ocnx pin. the output compare registers are 16-bit in size. to ensure that both the high and low bytes are written simultaneously when the cpu writes to these registers, the access is performed using an 8-bit temporary high byte register (temp). this temporary register is shared by al l the other 16-bit registers. see section 16.3 ?accessing 16-bit registers? on page 92 . 16.11.10 icr1h and icr1l ? input capture register 1 the input capture is updated with the counter (tcnt1) value each time an event occurs on the icpn pin (or optionally on the analog comparator output for timer/co unter1). the input capture can be used for defining the counter top value. the input capture register is 16-bit in size. to ensure that both the high and lo w bytes are read simultaneously when the cpu accesses these registers, th e access is performed using an 8-bit temporary high byte register (temp). this temporary register is shared by all th e other 16-bit registers. see section 16.3 ?accessing 16-bi t registers? on page 92 . bit 76543210 (0x8b) ocr1b[15:8] ocr1bh (0x8a) ocr1b[7:0] ocr1bl read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 (0x99) ocr3a[15:8] ocr3ah (0x98) ocr3a[7:0] ocr3al read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 (0x9b) ocr3b[15:8] ocr3bh (0x9a) ocr3b[7:0] ocr3bl read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 (0x87) icr1[15:8] icr1h (0x86) icr1[7:0] icr1l read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 115 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 16.11.11 icr3h and icr3l ? input capture register 3 the input capture is updated with the counter (tcnt3) value each time an event occurs on the icpn pin (or optionally on the analog comparator output for timer/co unter3). the input capture can be used for defining the counter top value. the input capture register is 16-bit in size. to ensure that both the high and lo w bytes are read simultaneously when the cpu accesses these registers, th e access is performed using an 8-bit temporary high byte register (temp). this temporary register is shared by all th e other 16-bit registers. see section 16.3 ?accessing 16-bi t registers? on page 92 . 16.11.12 timsk1 ? timer/counter1 interrupt mask register ? bit 7:6 ? reserved these bits are unused and will always read as zero. ? bit 5 ? icie1: timer/counter1 , input capture interrupt enable when this bit is written to one, and the i-flag in the status register is set (i nterrupts globally enabled), the timer/counter1 input capture interrupt is enabled. the corresponding interrupt vector (see section 12. ?interrupts? on page 49 ) is executed when the icf1 fl ag, located in tifr1, is set. ? bit 4:3 ? reserved these bits are unused and will always read as zero. ? bit 2 ? ocie1b: timer/counter1, outp ut compare b match interrupt enable when this bit is written to one, and the i-flag in the status register is set (i nterrupts globally enabled), the timer/counter1 output compare b match interrupt is enabled. the corresponding interrupt vector (see section 12. ?interrupts? on page 49 ) is executed when the ocf1b flag, located in tifr1, is set. ? bit 1 ? ocie1a: timer/counter1, outp ut compare a match interrupt enable when this bit is written to one, and the i-flag in the status register is set (i nterrupts globally enabled), the timer/counter1 output compare a match interrupt is enabled. the corresponding interrupt vector (see section 12. ?interrupts? on page 49 ) is executed when the ocf1a flag, located in tifr1, is set. ? bit 0 ? toie1: timer/counter1, overflow interrupt enable when this bit is written to one, and the i-flag in the status register is set (i nterrupts globally enabled), the timer/counter1 overflow interrupt is enabled. the corresponding interrupt vector (see section 11.3 ?watchdog timer? on page 44 ) is executed when the to v1 flag, located in tifr1, is set. bit 76543210 (0x97) icr3[15:8] icr3h (0x96) icr3[7:0] icr3l read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 (0x6f) ? ?icie1 ? ? ocie1b ocie1a toie1 timsk1 read/write r r r/w r r r/w r/w r/w initial value 0 0 0 0 0 0 0 0 atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 116 16.11.13 timsk3 ? timer/counter3 interrupt mask register ? bit 7:6 ? reserved these bits are unused and will always read as zero. ? bit 5 ? icie3: timer/counter3 , input capture interrupt enable when this bit is written to one, and the i-flag in the status register is set (i nterrupts globally enabled), the timer/counter1 input capture interrupt is enabled. the corresponding interrupt vector (see section 12. ?interrupts? on page 49 ) is executed when the icf3 fl ag, located in tifr3, is set. ? bit 4:3 ? reserved these bits are unused and will always read as zero. ? bit 2 ? ocie3b: timer/counter3, outp ut compare b match interrupt enable when this bit is written to one, and the i-flag in the status register is set (i nterrupts globally enabled), the timer/counter3 output compare b match interrupt is enabled. the corresponding interrupt vector (see section 12. ?interrupts? on page 49 ) is executed when the ocf3b flag, located in tifr3, is set. ? bit 1 ? ocie3a: timer/counter3, outp ut compare a match interrupt enable when this bit is written to one, and the i-flag in the status register is set (i nterrupts globally enabled), the timer/counter3 output compare a match interrupt is enabled. the corresponding interrupt vector (see section 12. ?interrupts? on page 49 ) is executed when the ocf3a flag, located in tifr3, is set. ? bit 0 ? toie3: timer/counter3, overflow interrupt enable when this bit is written to one, and the i-flag in the status register is set (i nterrupts globally enabled), the timer/counter3 overflow interrupt is enabled. the corresponding interrupt vector (see section 11.3 ?watchdog timer? on page 44 ) is executed when the to v3 flag, located in tifr3, is set. bit 76543210 (0x71) ? ?icie3 ? ? ocie3b ocie3a toie3 timsk3 read/write r r r/w r r r/w r/w r/w initial value 0 0 0 0 0 0 0 0 117 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 16.11.14 tifr1 ? timer/counter1 interrupt flag register ? bit 7:6 ? reserved these bits are unused and will always read as zero. ? bit 5 ? icf1: timer/counter1, input capture flag this flag is set when a capture event oc curs on the icp1 pin. when the input capt ure register (icr1) is set by the wgmn3:0 to be used as the top value, the icf1 flag is set when the counter reaches the top value. icf1 is automatically cleared when the input capture interrupt vector is executed. alternatively, icf1 can be cleared by writing a logic one to its bit location. ? bit 4:3 ? reserved these bits are unused and will always read as zero. ? bit 2 ? ocf1b: timer/counter1 , output compare b match flag this flag is set in the timer clock cycl e after the counter (tcnt1) value matches the output compare register b (ocr1b). note that a forced output compare (foc 1b) strobe will not set the ocf1b flag. ocf1b is automatically cleared when the ou tput compare match b interrupt vector is executed. alternatively, ocf1b can be cleared by writing a logic one to its bit location. ? bit 1 ? ocf1a: timer/counter1 , output compare a match flag this flag is set in the timer clock cycl e after the counter (tcnt1) value matches the output compare register a (ocr1a). note that a forced output compare (foc 1a) strobe will not set the ocf1a flag. ocf1a is automatically cleared when the ou tput compare match a interrupt vector is executed. alternatively, ocf1a can be cleared by writing a logic one to its bit location. ? bit 0 ? tov1: timer/counter1, overflow flag the setting of this flag is dependent of the wgmn3:0 bits setting. in normal and ctc modes, the tov1 flag is set when the timer overflows. refer to table 16-5 on page 111 for the tov1 flag behavior when using another wgmn3:0 bit setting. tov1 is automatically cleared when the ti mer/counter1 overflow inte rrupt vector is executed. alternatively, tov1 can be cleared by writing a logic one to its bit location. bit 76543210 0x16 (0x36) ? ?icf1 ? ? ocf1b ocf1a tov1 tifr1 read/write r r r/w r r r/w r/w r/w initial value00000000 atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 118 16.11.15 tifr3 ? timer/counter3 interrupt flag register ? bit 7:6 ? reserved these bits are unused and will always read as zero. ? bit 5 ? icf3: timer/counter3, input capture flag this flag is set when a capture event oc curs on the icp3 pin. when the input capt ure register (icr1) is set by the wgmn3:0 to be used as the top value, the icf3 flag is set when the counter reaches the top value. icf3 is automatically cleared when the input capture interrupt vector is executed. alternatively, icf3 can be cleared by writing a logic one to its bit location. ? bit 4:3 ? reserved these bits are unused and will always read as zero. ? bit 2 ? ocf3b: timer/counter3 , output compare b match flag this flag is set in the timer clock cycl e after the counter (tcnt3) value matches the output compare register b (ocr3b). note that a forced output compare (foc 3b) strobe will not set the ocf3b flag. ocf3b is automatically cleared when the ou tput compare match b interrupt vector is executed. alternatively, ocf3b can be cleared by writing a logic one to its bit location. ? bit 1 ? ocf3a: timer/counter3 , output compare a match flag this flag is set in the timer clock cycl e after the counter (tcnt3) value matches the output compare register a (ocr3a). note that a forced output compare (foc 3a) strobe will not set the ocf3a flag. ocf3a is automatically cleared when the ou tput compare match a interrupt vector is executed. alternatively, ocf3a can be cleared by writing a logic one to its bit location. ? bit 0 ? tov3: timer/counter1, overflow flag the setting of this flag is dependent of the wgmn3:0 bits setting. in normal and ctc modes, the tov3 flag is set when the timer overflows. refer to table 16-5 on page 111 for the tov3 flag behavior when using another wgmn3:0 bit setting. tov3 is automatically cleared when the ti mer/counter3 overflow inte rrupt vector is executed. alternatively, tov3 can be cleared by writing a logic one to its bit location. bit 76543210 0x18 (0x38) ? ?icf3 ? ? ocf3b ocf3a tov3 tifr3 read/write r r r/w r r r/w r/w r/w initial value00000000 119 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 17. 8-bit timer/counter2 with pw m and asynchronous operation 17.1 features single channel counter clear timer on compare match (auto reload) glitch-free, phase correct pulse width modulator (pwm) frequency generator 10-bit clock prescaler overflow and compare match interrupt sources (tov2, ocf2a and ocf2b) allows clocking from external 32khz watc h crystal independent of the i/o clock 17.2 overview timer/counter2 is a general purpose, single channel, 8-bit timer/counter module. a simplified block diagram of the 8-bit timer/counter is shown in figure 16-12 on page 108 . for the actual placement of i/o pins, see section 1. ?pin configurations? on page 3 . cpu accessible i/o regist ers, including i/o bits and i/o pins, are shown in bold. the device-specific i/o regist er and bit locations are listed in the section 17.11 ?register description? on page 132 . the power reduction timer/counter2 bit, prtim2, in section 10.12.3 ?prr0 ? power reduction register 0? on page 39 must be written to zero to enable timer/counter2 module. atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 120 figure 17-1. 8-bit timer/counter block diagram control logic tcntn timer/counter count clear direction clk tn clk i/o clk i/o clk asy ocrna ocrnb assrn synchronization unit tccrna tccrnb = prescaler top bottom synchronized status flags status flags asynchronous mode select (asn) tovn (int. req.) ocna (int. req.) waveform generation t/c oscillator fixed top value data bus = = = 0 ocna tosc1 tosc2 ocnb (int. req.) waveform generation ocnb 121 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 17.2.1 registers the timer/counter (tcnt2) and output compare register (o cr2a and ocr2b) are 8-bit registers. interrupt request (abbreviated to int.req.) signals are all visible in the timer interrupt flag register (tifr2). all interrupts are individually masked with the timer interrupt mask register (timsk2). tifr2 and timsk2 are not shown in the figure. the timer/counter can be clocked internally, via the prescale r, or asynchronously clocked from the tosc1/2 pins, as detailed later in this section. the asynchronous operation is controlled by the asynchronous status register (assr). the clock select logic block contro ls which clock source the timer/counter uses to increment (or decrement) its value. the timer/counter is inactive when no clock source is selected. the out put from the clock select logic is referred to as the timer clock (clk t2 ). the double buffered output compare regist er (ocr2a and ocr2b) are compared with the timer/counter value at all times. the result of the compare can be used by the waveform gene rator to generate a pwm or variable frequency output on the output compare pins (oc2a and oc2b). see section 17.5 ?output compare unit? on page 123 for details. the compare match event will also set the compare flag (ocf2a or ocf2b) which can be used to generate an output compare interrupt request. 17.2.2 definitions many register and bit references in this document are written in general form. a lower case ?n? replaces the timer/counter number, in this case 2. however, when using the register or bit defines in a pr ogram, the precise form must be used, i.e., tcnt2 for accessing timer/counter2 counter value and so on. the definitions in table 17-1 are also used extensively throughout the section. 17.3 timer/counter clock sources the timer/counter can be clocked by an internal synchronous or an external asynchronous clock source. the clock source clk t2 is by default equal to the mcu clock, clk i/o . when the as2 bit in the assr register is written to logic one, the clock source is taken from the timer/counter oscillator connected to tosc1 and tosc2. for details on asynchronous operation, see section 17.11.6 ?assr ? asynchrono us status register? on page 136 . for details on clock sources and prescaler, see section 17.10 ?timer/counter prescaler? on page 131 . table 17-1. definitions parameter definition bottom the counter reaches the bottom when it becomes zero (0x00). max the counter reaches its maximum when it becomes 0xff (decimal 255). top the counter reaches the top when it becomes equal to the highest value in the count sequence. the top value can be assigned to be the fixed value 0xff (max) or the value stored in the ocr2a register. the assignment is dependent on the mode of operation. atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 122 17.4 counter unit the main part of the 8-bit timer/counter is the programmable bi-directional counter unit. figure 17-2 shows a block diagram of the counter and its surrounding environment. figure 17-2. counter unit block diagram signal description (internal signals): count increment or decrement tcnt2 by 1. direction selects between increment and decrement. clear clear tcnt2 (set all bits to zero). clk tn timer/counter clock, referred to as clk t2 in the following. top signalizes that tcnt2 has reached maximum value. bottom signalizes that tcnt2 has r eached minimum value (zero). depending on the mode of operation used, t he counter is cleared, incremented, or decremented at each timer clock (clk t2 ). clk t2 can be generated from an external or internal clock source , selected by the clock select bits (cs22:0). when no clock source is selected (cs22:0 = 0) the time r is stopped. however, the tcnt2 value can be accessed by the cpu, regardless of whether clk t2 is present or not. a cpu write overrides (has pr iority over) all counter clear or count operations. the counting sequence is determined by the setting of the wgm21 and wgm20 bits located in the timer/counter control register (tccr2a) and the wgm22 located in the timer/counter contro l register b (tccr2b). th ere are close connections between how the counter behaves (counts) and how waveforms are generated on the output compare outputs oc2a and oc2b. for more details about advanced counting sequences and waveform generation, see section 17.7 ?modes of operation? on page 125 . the timer/counter overflow flag (tov2) is set according to t he mode of operation selected by the wgm22:0 bits. tov2 can be used for generating a cpu interrupt. top bottom tovn (int. req.) data bus control logic tcntn clk tn clear count direction clk i/o prescaler t/c oscillator tosc1 tosc2 123 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 17.5 output compare unit the 8-bit comparator continuously com pares tcnt2 with the output compare register (ocr2a and ocr2b). whenever tcnt2 equals ocr2a or ocr2b, the comparator signals a ma tch. a match will set the outpu t compare flag (ocf2a or ocf2b) at the next timer clo ck cycle. if the corresponding interrupt is enabled , the output compare fl ag generates an output compare interrupt. the output compare flag is automatically cleared when the interrupt is execut ed. alternatively, the output compare flag can be cleared by software by writing a logical one to its i/o bit location. the waveform generator uses the match signal to generate an output according to operatin g mode set by the wgm22:0 bits and compare output mode (com2x1:0) bits. the max and bottom signals are used by t he waveform generator for handling the special cases of the extreme values in some modes of operation (see section 17.7 ?modes of operation? on page 125 ). figure 16-10 on page 107 shows a block diagram of the output compare unit. figure 17-3. output comp are unit, block diagram the ocr2x register is double buffered when using any of the pulse width modulation (pwm) modes. for the normal and clear timer on compare (ctc) modes of operation, the doubl e buffering is disabled. the double buffering synchronizes the update of the ocr2x compare register to either top or bottom of the counting sequence. the synchronization prevents the occurrence of odd-length, non-symmetrical pwm pulses, thereby making the output glitch-free. the ocr2x register access may seem co mplex, but this is not case. when th e double buffering is enabled, the cpu has access to the ocr2x buffer register, and if double buffer ing is disabled the cpu will access the ocr2x directly. 17.5.1 force output compare in non-pwm waveform generation modes, the match output of the comparator can be forced by writing a one to the force output compare (foc2x) bit. forc ing compare match will not set the ocf2x flag or reload/clear the timer, but the oc2x pin will be updated as if a real compare match had occurred (the co m2x1:0 bits settings define w hether the oc2x pin is set, cleared or toggled). 17.5.2 compare match blocking by tcnt2 write all cpu write operations to the tcnt2 register will block any co mpare match that occurs in the next timer clock cycle, even when the timer is stopped. this feature allows ocr2x to be initialized to the same value as tcnt2 without triggering an interrupt when the timer/counter clock is enabled. ocfnx (int. req.) = (8-bit comparator) ocrnx waveform generator tcntn ocnx top bottom focn wgmn1:0 comnx1:0 data bus atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 124 17.5.3 using the ou tput compare unit since writing tcnt2 in any mode of ope ration will block all compare matches for one timer clock cycle, there are risks involved when changing tcnt2 when using the output compar e channel, independently of w hether the timer/counter is running or not. if the value written to tcnt2 equals the ocr2 x value, the compare match will be missed, resulting in incorrect waveform generation. similarly, do not write th e tcnt2 value equal to bottom when the counter is downcounting. the setup of the oc2x should be performed bef ore setting the data direction register for the port pin to output. the easiest way of setting the oc2x value is to use the force output co mpare (foc2x) strobe bit in normal mode. the oc2x register keeps its value even when changing between waveform generation modes. be aware that the com2x1:0 bits are not double buffered together with the compar e value. changing the com2x1:0 bits will take effect immediately. 17.6 compare match output unit the compare output mode (com2x1:0) bits have two functi ons. the waveform generator uses the com2x1:0 bits for defining the output compare (oc2x) state at the next compare match. also, the com2x1:0 bits control the oc2x pin output source. figure 17-4 shows a simplified schematic of the logic affected by the com2x1:0 bit setting. the i/o registers, i/o bits, and i/o pins in the figure are shown in bold. only the parts of the general i/o port control registers (ddr and port) that are affected by the com2x1:0 bits are shown. when referring to the oc2x st ate, the reference is for the internal oc2x register, not the oc2x pin. figure 17-4. compare match output unit, schematic the general i/o port function is overridden by the output co mpare (oc2x) from the waveform generator if either of the com2x1:0 bits are set. however, the oc2x pin direction (input or output) is still controlled by the data direction register (ddr) for the port pin. the data direction register bit for the oc2x pin (ddr_oc 2x) must be set as output before the oc2x value is visible on the pin. the port override func tion is independent of the waveform generation mode. the design of the output compare pin logic allows initialization of the oc2x state before the output is enabled. note that some com2x1:0 bit settings are reserved for certain modes of operation. see section 17.11 ?register description? on page 132 . data bus 0 1 q d comnx1 comnx0 focnx ocnx waveform generator q d port q d ddr ocnx pin clk i/o 125 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 17.6.1 compare output mode and waveform generation the waveform generator uses the com2x1:0 bits differentl y in normal, ctc, and pwm modes. for all modes, setting the com2x1:0 = 0 tells the waveform generator that no action on the oc2x register is to be performed on the next compare match. for compare output actions in the non-pwm modes refer to table 17-5 on page 133 . for fast pwm mode, refer to table 17-6 on page 133 , and for phase correct pwm refer to table 17-7 on page 134 . a change of the com2x1:0 bits state will have effect at the first compare match after the bi ts are written. for non-pwm modes, the action can be forced to have immedi ate effect by using the foc2x strobe bits. 17.7 modes of operation the mode of operation, i.e., t he behavior of the timer/counter and the output compare pins, is defined by the combination of the waveform generation mode (wgm22:0) and compare output mode (com2x1:0) bits. the compare output mode bits do not affect the counting sequence, while t he waveform generation mode bits do. the com2x1:0 bits control whether the pwm output generated should be inverted or not (inverted or non-inverted pwm). for non-p wm modes the com2x1:0 bits control whether the output should be set, clea red, or toggled at a compare match (see section 17.6 ?compare match output unit? on page 124 ). for detailed timing information refer to section 17.8 ?timer/counter timing diagrams? on page 129 . 17.7.1 normal mode the simplest mode of operation is t he normal mode (wgm22:0 = 0). in this mo de the counting direction is always up (incrementing), and no counter clear is performed. the coun ter simply overruns when it passes its maximum 8-bit value (top = 0xff) and then restarts from the bottom (0x00). in normal operation the ti mer/counter overflow flag (tov2) will be set in the same timer cl ock cycle as the tcnt2 becomes zero . the tov2 flag in this case behaves like a ninth bit, except that it is only set, not cleared. however, combined with the timer overflow interrupt that automatically clears the tov2 flag, the timer resolution can be increased by software. there are no special cases to consider in the normal mode, a new counter value can be written anytime. the output compare unit can be used to generate interrupts at some given time. using the output compare to generate waveforms in normal mode is not recommended, since this will occupy too much of the cpu time. 17.7.2 clear timer on compare match (ctc) mode in clear timer on compare or ctc mode (wgm22:0 = 2), the ocr2 a register is used to manipulate the counter resolution. in ctc mode the counter is cleared to zero when the counter value (tcnt2) matches the ocr2a. the ocr2a defines the top value for the counter, hence also its resolution. this mode allo ws greater control of the comp are match output frequency. it also simplifies the operation of counting external events. the timing diagram for the ctc mode is shown in table 17-5 on page 125 . the counter value (tcnt2) increases until a compare match occurs between tcnt2 and ocr2 a, and then counter (tcnt2) is cleared. figure 17-5. ctc mode, timing diagram 12 tcntn (comnx1:0 = 1) ocnx (toggle) period 3 ocnx interrupt flag set 4 atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 126 an interrupt can be generated each time the counter value reac hes the top value by using the ocf2a flag. if the interrupt is enabled, the interrupt handler routine can be used for updat ing the top value. however, changing top to a value close to bottom when the counter is running with non e or a low prescaler value must be done with care since the ctc mode does not have the double buffering feat ure. if the new value written to ocr2a is lower than the current value of tcnt2, the counter will miss the compare match. the counter will then have to count to its maximum value (0xff) and wrap around starting at 0x00 before the compare match can occur. for generating a waveform output in ctc mode, the oc2a output can be set to to ggle its logical level on each compare match by setting the compare output mode bits to toggle mode (com2a1:0 = 1). the oc2a value will not be visible on the port pin unless the data direction for the pin is set to out put. the waveform generated will have a maximum frequency of f oc2a = f clk_i/o /2 when ocr2a is set to zero (0x00). the wave form frequency is defined by the following equation: the n variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024). as for the normal mode of oper ation, the tov2 flag is set in the same timer clock cycle that the counter counts from max to 0x00. 17.7.3 fast pwm mode the fast pulse width modulation or fast pwm mode (wgm22: 0 = 3 or 7) provides a high frequency pwm waveform generation option. the fast pwm differs from the other pwm optio n by its single-slope operation. the counter counts from bottom to top then restarts from bottom. top is defined as 0xff when wgm22:0 = 3, and ocr2a when mgm22:0 = 7. in non-inverting compare out put mode, the output compar e (oc2x) is cleared on the compare match between tcnt2 and ocr2x, and set at bottom. in inverting compar e output mode, the output is set on compare match and cleared at bottom. due to the single-sl ope operation, the operating frequency of t he fast pwm mode can be twice as high as the phase correct pwm mode that uses dual-slope operation. this high frequen cy makes the fast pwm mode well suited for power regulation, rectification, and da c applications. high frequency allows physically small sized external components (coils, capacitors), and theref ore reduces total system cost. in fast pwm mode, the counter is incremen ted until the counter value ma tches the top value. the counter is then cleared at the following timer clock cycle. the timing diagram for the fast pwm mode is shown in figure 17-6 . the tcnt2 value is in the timing diagram shown as a histogram for illustrating the single-slope operation. the diagram includes non-inverted and inverted pwm outputs. the sm all horizontal line marks on the tcnt2 slopes represent compare matches between ocr2x and tcnt2. figure 17-6. fast pwm mode, timing diagram f ocnx f clk_i/o 2 n 1 ocrnx + () ?? ------------------------------------------------ - = 1234567 tcntn (comnx1:0 = 2) (comnx1:0 = 3) ocnx ocnx period ocrnx update and tovn interrupt flag set ocrnx interrupt flag set 127 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 the timer/counter overflow flag (tov2) is set each time the co unter reaches top. if the inte rrupt is enabled, the interrupt handler routine can be used fo r updating the compare value. in fast pwm mode, the compare unit allo ws generation of pwm waveforms on the oc2x pin. setting the com2x1:0 bits to two will produce a non-inverted pwm and an inverted pwm output can be generated by setting the com2x1:0 to three. top is defined as 0xff when wgm2:0 = 3, and ocr2a when wgm2:0 = 7 (see table 17-3 on page 132 ). the actual oc2x value will only be visible on the port pin if the data direction for the port pin is set as output. the pwm waveform is generat ed by setting (or clearing) the oc2x regist er at the compare match between ocr2x and tcnt2, and clearing (or setting) the oc2x register at the timer cl ock cycle the counter is cleared (changes from top to bottom). the pwm frequency for the output can be calculated by the following equation: the n variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024). the extreme values for the ocr2a regist er represent special cases when generating a pwm waveform output in the fast pwm mode. if the ocr2a is set equal to bottom, the output will be a narrow sp ike for each max+1 timer clock cycle. setting the ocr2a equal to max will result in a constantly high or low output (depending on the pol arity of the output set by the com2a1:0 bits.) a frequency (with 50% duty cycle) waveform output in fast pw m mode can be achieved by settin g oc2x to togg le its logical level on each compare match (com2x1:0 = 1). the waveform generated will have a maximum frequency of f oc2 = f clk_i/o /2 when ocr2a is set to zero. this feature is similar to the oc 2a toggle in ctc mode, except the double buffer feature of the output compare unit is enabled in the fast pwm mode. 17.7.4 phase correct pwm mode the phase correct pwm mode (wgm22:0 = 1 or 5) provides a high resolution phase correct pwm waveform generation option. the phase correct pwm mode is based on a dual-slope operation. the counter count s repeatedly from bottom to top and then from top to bottom. top is defined as 0x ff when wgm22:0 = 1, and ocr2a when mgm22:0 = 5. in non-inverting compare output mode, the output compare (oc2x) is cleared on the compare match between tcnt2 and ocr2x while upcounting, and set on the compare match while downcounting. in inverting output compare mode, the operation is inverted. the dual-slope operation has lowe r maximum operation frequency than single slope operation. however, due to the symmetric feature of the dual-slo pe pwm modes, these modes are preferred for motor control applications. in phase correct pwm mode the counter is incremented until the counter value matches top. when the counter reaches top, it changes the count direct ion. the tcnt2 value will be equal to top for one timer clock cycle. the timing diagram for the phase correct pwm mode is shown on figure 17-7 on page 128 . the tcnt2 value is in the timing diagram shown as a histogram for illustrating the dual-slope o peration. the diagram includes non-inve rted and inverted pwm outputs. the small horizontal line marks on the tcnt2 slopes repr esent compare matches between ocr2x and tcnt2. f ocnxpwm f clk_i/o n 256 ? ----------------- = atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 128 figure 17-7. phase correct pwm mode, timing diagram the timer/counter overflow flag (tov2) is set each time the counter reaches bottom. the interrupt flag can be used to generate an interrupt each time the counter reaches the bottom value. in phase correct pwm mode, the compare unit allows ge neration of pwm waveforms on the oc2x pin. setting the com2x1:0 bits to two will produce a non-inverted pwm. an inverted pwm output can be generated by setting the com2x1:0 to three. top is defined as 0xff when wgm2:0 = 3, and ocr2a when mgm2:0 = 7 (see table 17-4 on page 133 ). the actual oc2x value will only be visible on the port pi n if the data direction for t he port pin is set as output. the pwm waveform is generated by clearing (or setting) th e oc2x register at the compare match between ocr2x and tcnt2 when the counter increments, and setting (or clearing) the oc2x register at com pare match between ocr2x and tcnt2 when the counter decrements. the pwm frequency for t he output when using phase co rrect pwm can be calculated by the following equation: the n variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024). the extreme values for the ocr2a regist er represent special cases when generating a pwm waveform output in the phase correct pwm mode. if the ocr2a is set equal to bottom, the output will be continuously low and if set equal to max the output will be continuously high for no n-inverted pwm mode. for inverted pwm the output will have the opposite logic values. at the very start of period 2 in figure 17-7 ocnx has a transition from high to lo w even though there is no compare match. the point of this transition is to gua rantee symmetry around bottom. there are tw o cases that give a transition without compare match. ocr2a changes its value from max, like in figure 17-7 . when the ocr2a value is max the ocn pin value is the same as the result of a down-counting compare match. to ensure symmetry around bottom the ocn value at max must correspond to the result of an up-counting compare match. the timer starts counting from a value higher than the on e in ocr2a, and for that reason misses the compare match and hence the ocn change that would have happened on the way up. 123 tcntn (comnx1:0 = 2) (comnx1:0 = 3) ocnx ocnx period tovn interrupt flag set ocrnx update ocnx interrupt flag set f ocnxpcpwm f clk_i/o n 510 ? ----------------- = 129 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 17.8 timer/counter timing diagrams the following figures show the timer/counter in synchronous mode, and the timer clock (clk t2 ) is therefore shown as a clock enable signal. in asynchronous mode, clk i/o should be replaced by the timer/counter oscillator clock. the figures include information on when interrupt flags are set. figure 17-8 contains timing data for basic ti mer/counter operation. the figure shows the count sequence close to the max value in all modes other than phase correct pwm mode. figure 17-8. timer/counter timing diagram, no prescaling figure 17-9 shows the same timing data, but with the prescaler enabled. figure 17-9. timer/counter timing diagram, with prescaler (f clk_i/o /8) figure 17-10 shows the setting of ocf2a in all modes except ctc mode. figure 17-10. timer/counter timing diagra m, setting of ocf2a, with prescaler (f clk_i/o /8) max - 1 clk i/o (clk i/o /1) tcntn tovn clk tn max bottom bottom + 1 max - 1 clk i/o (clk i/o /8) tcntn tovn clk tn max bottom bottom + 1 ocrnx - 1 clk i/o (clk i/o /8) tcntn ocrnx ocfnx clk tn ocrnx ocrnx + 1 ocrnx value ocrnx + 2 atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 130 figure 17-11 shows the setting of ocf2a and the clearing of tcnt2 in ctc mode. figure 17-11. timer/counter timing diagram, clear timer on compar e match mode, with prescaler (f clk_i/o /8) 17.9 asynchronous operation of timer/counter2 when timer/counter2 operates asynchronously, some considerations must be taken. warning: when switching between asynchronous and synch ronous clocking of timer/counter2, the timer registers tcnt2, ocr2x, and tccr2x might be corrupted. a safe procedure for switching clock source is: 1. disable the timer/counter2 interrupts by clearing ocie2x and toie2. 2. select clock source by setting as2 as appropriate. 3. write new values to tcnt2, ocr2x, and tccr2x. 4. to switch to asynchronous operation: wait for tcn2ub, ocr2xub, and tcr2xub. 5. clear the timer/coun ter2 interrupt flags. 6. enable interrupts, if needed. the cpu main clock frequency must be more than four times the oscillator frequency. when writing to one of the registers t cnt2, ocr2x, or tccr2x, t he value is transferred to a temporary register, and latched after two positive edges on tosc1. the user should not write a new value before the contents of the temporary register have been tran sferred to its destination. each of the five mentioned registers have their individual temporary register, which means that e.g. writing to tcnt2 does not disturb an ocr2x write in progress. to detect that a transfer to the dest ination register has taken place, the a synchronous status regi ster ? assr has been implemented. when entering power-save or adc noise reduction mode af ter having written to tcnt2, ocr2x, or tccr2x, the user must wait until the written register has been updated if timer/counter2 is used to wake up the device. otherwise, the mcu will enter sleep mode before the ch anges are effective. this is particul arly important if any of the output compare2 interrupt is used to wake up the device, since the output compare f unction is disabled during writing to ocr2x or tcnt2. if the write cycle is not finished, and the mcu enters sleep mode before the corresponding ocr2xub bit returns to zero, the device will never receive a compare match interrupt, and the mcu will not wake up. if timer/counter2 is used to wake the device up from po wer-save or adc noise reduction mode, precautions must be taken if the user wants to re-enter one of these modes: the interrupt logic needs one tosc1 cycle to be reset. if the time between wake-up and re-entering sleep mode is less than one tosc1 cycle, the interrupt will not occur, and the device will fail to wake up. if the user is in doubt wh ether the time before re-entering power-save or adc noise reduction mode is sufficient, the following algorithm can be used to ensure that one tosc1 cycle has elapsed: 1. write a value to tccr2x, tcnt2, or ocr2x. 2. wait until the correspon ding update busy flag in assr returns to zero. 3. enter power-save or adc noise reduction mode. top - 1 clk i/o (clk i/o /8) tcntn (ctc) ocrnx ocfnx clk tn top bottom top bottom + 1 131 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 when the asynchronous operation is sele cted, the 32.768khz oscillator for timer/ counter2 is always running, except in power-down and standby modes. after a power-up reset or wake-up from power-down or standby mode, the user should be aware of the fact that this oscillator might take as long as one second to stabilize. the user is advised to wait for at least one second before using timer/counter2 after power-up or wake-up from power-down or standby mode. the contents of all timer/counter2 registers must be considered lost after a wake-up from power-down or standby mode due to unstable clock signal upon start-up, no ma tter whether the oscillator is in use or a clock signal is applied to the tosc1 pin. description of wake up from power-save or adc noise reduction mode when the timer is clocked asynchronously: when the interrupt condition is met, the wake up process is st arted on the following cycle of the timer clock, that is, the timer is always advanced by at least one before the processor can read the counte r value. after wake-up, the mcu is halted for four cycles, it execut es the interrupt routine, and resumes execution from the instruction following sleep. reading of the tcnt2 register shortly after wake-up from power-save may give an incorrect result. since tcnt2 is clocked on the asynchronous tosc clock, reading tcnt 2 must be done through a register synchronized to the internal i/o clock domain. synchronization takes plac e for every rising tosc1 edge. when waking up from power-save mode, and the i/o clock (clk i/o ) again becomes active, tcnt2 will read as the previous value (before entering sleep) until the next rising tosc1 edge. the phas e of the tosc clock after waking up from power-save mode is essentially unpredictable, as it depends on the wake-up time. the recommended procedure for reading tcnt2 is thus as follows: 1. write any value to either of the registers ocr2x or tccr2x. 2. wait for the corresponding update busy flag to be cleared. 3. read tcnt2. during asynchronous operation, the synchronization of the interrupt flags for the asynchronous timer takes 3 processor cycles plus one timer cycle. the timer is therefore advanced by at least one before the processor can read the timer value causing the setting of the interrupt flag. the output compare pin is changed on the timer clock and is not synchronized to the processor clock. 17.10 timer/counter prescaler figure 17-12.prescaler for timer/counter2 timer/counter2 clock source clk t2 clk t2s /8 clk t2s /32 clk t2s /64 clk t2s /128 clk t2s /256 clk t2s /1024 clk i/o tosc1 as2 psrasy clk t2s 10-bit t/c prescaler 0 clear cs20 cs21 cs22 atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 132 the clock source for timer/counter2 is named clk t2s . clk t2s is by default conn ected to the main system i/o clock clk i o . by setting the as2 bit in assr, timer/counte r2 is asynchronously clocked from the tosc1 pin. this enables use of timer/counter2 as a real time counter (rtc). when as2 is set, pins tosc1 and tosc2 are disconnected from port c. a crystal can then be connected between the tosc1 and to sc2 pins to serve as an independent clock source for timer/counter2. th e oscillator is optimized for use with a 32.768khz crystal. by setting the exclk bit in the assr a 32khz external clock can be applied. see section 17.11.6 ?assr ? asynchrono us status register? on page 136 for details. for timer/counter2, the possible prescaled selections are: clk t2s /8, clk t2s /32, clk t2s /64, clk t2s /128, clk t2s /256, and clk t2s /1024. additionally, clk t2s as well as 0 (stop) may be selected. setting the psrasy bit in gtccr resets the prescaler. this allows the user to operate with a predictable prescaler. 17.11 register description 17.11.1 tccr2a ? timer/count er control register a ? bits 7:6 ? com2a1:0: compare match output a mode these bits control the output compare pin (oc2a) behavior. if o ne or both of the com2a1:0 bits are set, the oc2a output overrides the normal port functionality of th e i/o pin it is connected to. however, not e that the data direction register (ddr) bit corresponding to the oc2a pin must be set in order to enable the output driver. when oc2a is connected to the pin, the function of the com2a1:0 bits depends on the wgm22:0 bit setting. table 17-2 shows the com2a1:0 bit functionality when the wgm22:0 bits are set to a normal or ctc mode (non-pwm). table 17-3 shows the com2a1:0 bit functionality when the wgm21:0 bits are set to fast pwm mode. bit 7 6 5 4 3 210 (0xb0) com2a1 com2a0 com2b1 com2b0 ? ? wgm21 wgm20 tccr2a read/write r/w r/w r/w r/w r r r/w r/w initial value 0 0 0 0 0 0 0 0 table 17-2. compare output mode, non-pwm mode com2a1 com2a0 description 0 0 normal port operation, oc0a disconnected. 0 1 toggle oc2a on compare match 1 0 clear oc2a on compare match 1 1 set oc2a on compare match table 17-3. compare output mode, fast pwm mode (1) com2a1 com2a0 description 0 0 normal port operation, oc2a disconnected. 0 1 wgm22 = 0: normal port op eration, oc0a disconnected. wgm22 = 1: toggle oc2a on compare match. 1 0 clear oc2a on compare match, set oc2a at bottom, (non-inverting mode). 1 1 set oc2a on compare match, clear oc2a at bottom, (inverting mode). note: 1. a special case occurs when ocr2a equals top and com2a1 is set. in this case, the compare match is ignored, but the set or clear is done at bottom. see section 17.7.3 ?fast pwm mode? on page 126 for more details. 133 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 table 17-4 shows the com2a1:0 bit functionality when the wgm22:0 bits are set to phase correct pwm mode. ? bits 5:4 ? com2b1:0: compare match output b mode these bits control the output compare pin (oc2b) behavior. if o ne or both of the com2b1:0 bits are set, the oc2b output overrides the normal port functionality of th e i/o pin it is connected to. however, not e that the data direction register (ddr) bit corresponding to the oc2b pin must be set in order to enable the output driver. when oc2b is connected to the pin, the function of the com2b1:0 bits depends on the wgm22:0 bit setting. table 17-5 shows the com2b1:0 bit functionality when the wgm22:0 bits are set to a normal or ctc mode (non-pwm). table 17-6 shows the com2b1:0 bit functionality when the wgm22:0 bits are set to fast pwm mode. table 17-4. compare output mode, phase correct pwm mode (1) com2a1 com2a0 description 0 0 normal port operation, oc2a disconnected. 0 1 wgm22 = 0: normal port operation, oc2a disconnected. wgm22 = 1: toggle oc2a on compare match. 1 0 clear oc2a on compare match when up-counting. set oc2a on compare match when down-counting. 1 1 set oc2a on compare match when up-counting. clear oc2a on compare match when down-counting. note: 1. a special case occurs when ocr2a equals top and com2a1 is set. in this case, the compare match is ignored, but the set or clear is done at top. see section 17.7.4 ?phase correct pwm mode? on page 127 for more details. table 17-5. compare output mode, non-pwm mode com2b1 com2b0 description 0 0 normal port operation, oc2b disconnected. 0 1 toggle oc2b on compare match 1 0 clear oc2b on compare match 1 1 set oc2b on compare match table 17-6. compare output mode, fast pwm mode (1) com2b1 com2b0 description 0 0 normal port operation, oc2b disconnected. 0 1 reserved 1 0 clear oc2b on compare match, set oc2b at bottom, (non-inverting mode). 1 1 set oc2b on compare match, clear oc2b at bottom, (inverting mode). note: 1. a special case occurs when ocr2b equals top and com2b1 is set. in this case, the compare match is ignored, but the set or clear is done at bottom. see section 17.7.3 ?fast pwm mode? on page 126 for more details. atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 134 table 17-7 shows the com2b1:0 bit functionality when the wgm22:0 bits are set to phase correct pwm mode. ? bits 3:2 ? reserved these bits are reserved and will always read as zero. ? bits 1:0 ? wgm21:0: waveform generation mode combined with the wgm22 bit found in the t ccr2b register, these bits control the counting sequence of the counter, the source for maximum (top) counter value, and w hat type of waveform generation to be used, see table 17-8 . modes of operation supported by the timer/counter unit are: normal mode (counter), clear ti mer on compare match (ctc) mode, and two types of pulse width modulation (pwm) modes (see section 17.7 ?modes of operation? on page 125 ). table 17-7. compare output mode, phase correct pwm mode (1) com2b1 com2b0 description 0 0 normal port operation, oc2b disconnected. 0 1 reserved 1 0 clear oc2b on compare match when up-counting. set oc2b on compare match when down-counting. 1 1 set oc2b on compare match when up-counting. clear oc2b on compare match when down-counting. note: 1. a special case occurs when ocr2b equals top and com2b1 is set. in this case, the compare match is ignored, but the set or clear is done at top. see section 17.7.4 ?phase correct pwm mode? on page 127 for more details. table 17-8. waveform generation mode bit description mode wgm2 wgm1 wgm0 timer/counter mode of operation top update of ocrx at tov flag set on (1)(2) 0 0 0 0 normal 0xff immediate max 1 0 0 1 pwm, phase correct 0xff top bottom 2 0 1 0 ctc ocra immediate max 3 0 1 1 fast pwm 0xff bottom max 4 1 0 0 reserved ? ? ? 5 1 0 1 pwm, phase correct ocra top bottom 6 1 1 0 reserved ? ? ? 7 1 1 1 fast pwm ocra bottom top notes: 1. max = 0xff 2. bottom = 0x00 135 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 17.11.2 tccr2b ? timer/count er control register b ? bit 7 ? foc2a: force output compare a the foc2a bit is only active when the wgm bits specify a non-pwm mode. however, for ensuring compatibility with future devices, this bit must be set to zero when tccr2b is written when operating in pwm mode. when writing a logical one to the foc2a bi t, an immediate compare match is forced on the waveform generation unit. the oc2a output is changed according to its com2a1:0 bits setting. note that the foc2a bit is implemented as a strobe. therefor e it is the value present in the com2a1:0 bits that determ ines the effect of the forced compare. a foc2a strobe will not generate any interrupt, nor will it clear the timer in ctc mode using ocr2a as top. the foc2a bit is always read as zero. ? bit 6 ? foc2b: force output compare b the foc2b bit is only active when the wgm bits specify a non-pwm mode. however, for ensuring compatibility with future devices, this bit must be set to zero when tccr2b is written when operating in pwm mode. when writing a logical one to the foc2b bi t, an immediate compare match is forced on the waveform generation unit. the oc2b output is changed according to its com2b1:0 bits setting. note that the foc2b bit is implemented as a strobe. therefor e it is the value present in the com2b1:0 bits that determ ines the effect of the forced compare. a foc2b strobe will not generate any interrupt, nor will it clear the timer in ctc mode using ocr2b as top. the foc2b bit is always read as zero. ? bits 5:4 ? reserved these bits are reserved and will always read as zero. ? bit 3 ? wgm22: waveform generation mode see the description in section 17.11.1 ?tccr2a ? timer/counter control register a? on page 132 . ? bit 2:0 ? cs22:0: clock select the three clock sele ct bits select the clock source to be used by the timer/counter, see table 17-9 . bit 7 6 5 4 3 2 1 0 (0xb1) foc2a foc2b ? ? wgm22 cs22 cs21 cs20 tccr2b read/write w w r r r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 table 17-9. clock select bit description cs22 cs21 cs20 description 0 0 0 no clock source (timer/counter stopped). 0 0 1 clk t2s /(no prescaling) 0 1 0 clk t2s /8 (from prescaler) 0 1 1 clk t2s /32 (from prescalerf 1 0 0 clk t2s /64 (from prescaler) 1 0 1 clk t2s /128 (from prescaler) 1 1 0 clk t 2 s /256 (from prescaler) 1 1 1 clk t 2 s /1024 (from prescaler) atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 136 17.11.3 tcnt2 ? timer/counter register the timer/counter register gives direct a ccess, both for read and write operations, to the timer/counter unit 8-bit counter. writing to the tcnt2 register blocks (re moves) the compare match on the followin g timer clock. modifying the counter (tcnt2) while the counter is running, introduces a risk of missing a compare match between tcnt2 and the ocr2x registers. 17.11.4 ocr2a ? output compare register a the output compare register a contains an 8-bit value that is continuou sly compared with the counter value (tcnt2). a match can be used to generate an output compare interrup t, or to generate a waveform output on the oc2a pin. 17.11.5 ocr2b ? output compare register b the output compare register b contains an 8-bit value that is continuou sly compared with the counter value (tcnt2). a match can be used to generate an output compare interrup t, or to generate a waveform output on the oc2b pin. 17.11.6 assr ? asynchronous status register ? bit 6 ? exclk: enable external clock input when exclk is written to one, and asynchronous clock is selected, the external clock input buffer is enabled and an external clock can be input on timer oscillator 1 (tosc1) pi n instead of a 32khz crystal. writing to exclk should be done before asynchronous operation is selected. note that the cr ystal oscillator will only run when this bit is zero. ? bit 5 ? as2: asynch ronous timer/counter2 when as2 is written to zero, timer/counte r2 is clocked from the i/o clock, clk i/o . when as2 is written to one, timer/counter2 is clocked from a crystal oscillator connected to the timer oscill ator 1 (tosc1) pin. when the value of as2 is changed, the contents of tcnt2, ocr2a, o cr2b, tccr2a and tccr2b might be corrupted. ? bit 4 ? tcn2ub: timer/counter2 update busy when timer/counter2 operates asynchronously and tcnt2 is written, this bit becomes set. when tcnt2 has been updated from the temporary storage register, this bit is cleared by hardware. a logical zero in this bit indicates that tcnt2 i s ready to be updated with a new value. bit 76543210 (0xb2) tcnt2[7:0] tcnt2 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 (0xb3) ocr2a[7:0] ocr2a read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 (0xb4) ocr2b[7:0] ocr2b read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 7 6 5 4 3 2 1 0 (0xb6) ? exclk as2 tcn2ub ocr2aub ocr2bub tcr2aub tcr2bub assr read/write r r/w r/w r r r r r initial value 0 0 0 0 0 0 0 0 137 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 ? bit 3 ? ocr2aub: output compare register2 update busy when timer/counter2 operates asynchronously and ocr2a is written, this bit becomes set. when ocr2a has been updated from the temporary st orage register, this bit is cleared by hardware. a logical zero in this bi t indicates that ocr2a i s ready to be updated with a new value. ? bit 2 ? ocr2bub: output compare register2 update busy when timer/counter2 operates asynchronously and ocr2b is written, this bit becomes set. when ocr2b has been updated from the temporary st orage register, this bit is cleared by hardware. a logical zero in this bi t indicates that ocr2b i s ready to be updated with a new value. ? bit 1 ? tcr2aub: timer/counter control register2 update busy when timer/counter2 operates asynchronously and tccr2a is written, this bit becomes set. when tccr2a has been updated from the temporary st orage register, this bit is cleared by hardware. a logical zero in this bit indicates that tccr2a is ready to be updated with a new value. ? bit 0 ? tcr2bub: timer/counter control register2 update busy when timer/counter2 operates asynchronously and tccr2b is written, this bit becomes set. when tccr2b has been updated from the temporary st orage register, this bit is cleared by hardware. a logical zero in this bit indicates that tccr2b is ready to be updated with a new value. if a write is performed to any of the five timer/counter2 registers while its update busy flag is set, the updated value might get corrupted and cause an unintentional interrupt to occur. the mechanisms for reading tcnt2, o cr2a, ocr2b, tccr2a and tccr2b are different. when reading tcnt2, the actual timer value is read. when read ing ocr2a, ocr2b, tccr2a and tccr2b the value in the temporary storage register is read. 17.11.7 timsk2 ? timer/counter2 interrupt mask register ? bit 2 ? ocie2b: timer/counter2 outp ut compare match b interrupt enable when the ocie2b bit is written to one and the i-bit in the stat us register is set (one), the timer/counter2 compare match b interrupt is enabled. the corresponding interrupt is executed if a compare match in timer/coun ter2 occurs, i.e., when the ocf2b bit is set in the timer/counter 2 interrupt flag register ? tifr2. ? bit 1 ? ocie2a: timer/counter2 outp ut compare match a interrupt enable when the ocie2a bit is written to one and the i-bit in the stat us register is set (one), the timer/counter2 compare match a interrupt is enabled. the corresponding interrupt is executed if a compare match in timer/coun ter2 occurs, i.e., when the ocf2a bit is set in the timer/counter 2 interrupt flag register ? tifr2. ? bit 0 ? toie2: timer/counter2 overflow interrupt enable when the toie2 bit is written to one and the i-bit in the status register is set (one ), the timer/counter2 overflow interrupt i s enabled. the corresponding interrupt is exec uted if an overflow in timer/counter2 oc curs, i.e., when the tov2 bit is set in the timer/counter2 interrupt flag register ? tifr2. bit 76543 2 1 0 (0x70) ? ? ? ? ? ocie2b ocie2a toie2 timsk2 read/write r rrrr r/wr/wr/w initial value00000 0 0 0 atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 138 17.11.8 tifr2 ? timer/counte r2 interrupt flag register ? bit 2 ? ocf2b: output compare flag 2 b the ocf2b bit is set (one) when a compare match occurs between the timer/counter2 and the data in ocr2b ? output compare register2. ocf2b is cleared by hardware when executing the corresponding interrupt handling vector. alternatively, ocf2b is cleared by writing a logic one to the flag. when the i-bit in sreg, ocie2b (timer/counter2 compare match interrupt enable), and ocf2b are set (one), the timer/counter2 compare matc h interrupt is executed. ? bit 1 ? ocf2a: output compare flag 2 a the ocf2a bit is set (one) when a compare match occurs between the timer/counter2 and the data in ocr2a ? output compare register2. ocf2a is cleared by hardware when executing the corresponding interrupt handling vector. alternatively, ocf2a is cleared by writing a logic one to the flag. when the i-bit in sreg, ocie2a (timer/counter2 compare match interrupt enable), and ocf2a are set (one), the timer/counter2 compare matc h interrupt is executed. ? bit 0 ? tov2: timer/counter2 overflow flag the tov2 bit is set (one) when an overflow occurs in time r/counter2. tov2 is cleared by hardware when executing the corresponding interrupt handling vector. al ternatively, tov2 is cleared by writ ing a logic one to the flag. when the sreg i-bit, toie2a (timer/counter2 ov erflow interrupt enable), and tov2 are set (one), the timer/counter2 overflow interrupt is executed. in pwm mode, this bit is set when timer/counter2 changes counting direction at 0x00. 17.11.9 gtccr ? general timer/counter control register ? bit 7 ? tsm: timer/counter synchronization mode writing the tsm bit to one, activates the ti mer/counter synchronization mode. in this mode, the value that is written to the psrasy and psrsync bits is kept, hence keeping the corresponding prescaler reset signals asserted. this ensures that the corresponding timer/counters are halted and can be conf igured to the same value without the risk of one of them advancing during configuration. when the tsm bit is written to zero, the psrasy and psrsync bits are cleared by hardware, and the time r/counters start counting simultaneously. ? bit 1 ? psrasy: prescaler reset timer/counter2 when this bit is one, the timer/counter2 prescaler will be reset. this bit is normally cleared immediately by hardware. if the bit is written when timer/counter2 is operating in asynchronou s mode, the bit will remain one until the prescaler has been reset. the bit will not be cleared by hardware if the tsm bit is set. refer to the description of the ?bit 7 ? tsm: timer/count er synchronization mode? on this page for a description of the timer/counter synchronization mode. ? bit 0 ? psrsync: prescaler reset when this bit is one, timer/counter1 and timer/counter0 presca ler will be reset. this bit is normally cleared immediately by hardware, except ifthe tsm bit is set. no te that timer/counter1 and timer/counter0 share the same prescaler and a reset of this prescaler will affect both timers. bit 76543210 0x17 (0x37) ? ? ? ? ? ocf2b ocf2a tov2 tifr2 read/write rrrrrr/wr/wr/w initial value00000000 bit 7 6 5 4 3 2 1 0 0x23 (0x43) tsm ? ? ? ? ? psrasy psrsync gtccr read/write r/w r r r r r r/w r/w initial value 0 0 0 0 0 0 0 0 139 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 18. spi ? serial peripheral interface 18.1 features full-duplex, three-wire synchronous data transfer master or slave 0peration lsb first or msb first data transfer seven programmable bit rates end of transmission interrupt flag write collision flag protection wake-up from idle mode double speed (ck/2) master spi mode 18.2 overview the serial peripheral interface (spi) allows hi gh-speed synchronous data transfer between the atmel ? atmega164p-b/324p-b/644p-b and peri pheral devices or between several avr ? devices. usart can also be used in master spi mode, see section 20. ?usart in spi mode? on page 169 . the power reduction spi bit, prspi, in section 10.12.3 ?prr0 ? power reduction register 0? on page 39 must be written to zero to enable spi module. figure 18-1. spi block diagram (1) note: 1. refer to figure 1-1 on page 3 , and table 14-6 on page 65 for spi pin placement. 8-bit shift register read data buffer spi control register spi status register mstr spi clock (master) spe spi control spi interrupt request select clock logic miso clock 8 88 s m s m m s msb lsb spie spe wcol spif spi2x spi2x spr1 mstr spe dord spr0 dord mstr cpol cpha spr1 spr0 mosi sck ss divider /2/4/8/16/32/64/128 xtal internal data bus pin control logic atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 140 the interconnection between master and slave cpus with spi is shown in figure 18-2 . the system consists of two shift registers, and a master clock generator. the spi master initiates t he communication cycle when pulling low the slave select ss pin of the desired slave. master and slav e prepare the data to be sent in their re spective shift regist ers, and the master generates the required clock pulses on the sck line to interchange data. data is always shifted from master to slave on the master out ? slave in, mosi, line, and from slave to master on the master in ? slave out, miso, line. after each data packet, the master will synchronize the slave by pulling high the slave select, ss , line. when configured as a master, the spi in terface has no automatic control of the ss line. this must be handled by user software before communication can start. when this is done, writing a byte to the spi data register starts the spi clock generator, and the hardware shifts the eight bits into the slave. after shif ting one byte, the spi clock generator stops, setti ng the end of transmission flag (spif). if the spi interrupt enable bit (spie) in the spcr register is set, an interrupt is requested. the master may continue to shift t he next byte by writing it into spdr, or signal the end of packet by pulling high the slave select, ss line. the last incoming byte will be ke pt in the buffer register for later use. when configured as a slave, the spi interface will rema in sleeping with miso tri- stated as long as the ss pin is driven high. in this state, software may update the contents of the spi data register, spdr, but the data will not be shifted out by incoming clock pulses on the sck pin until the ss pin is driven low. as one byte has been completely shifted, the end of transmission flag, spif is set. if the spi interrupt enable bit, spie, in the spcr r egister is set, an interrupt is requested. the slave may continue to place new data to be sent into spdr befor e reading the incoming data. the last incoming byte will be kept in the buffer register for later use. figure 18-2. spi master-slave interconnection the system is single buffered in the transmi t direction and double buffered in the receive directio n. this means that bytes to be transmitted cannot be written to the spi data register before the entire shift cycle is co mpleted. when receiving data, however, a received character must be read from the spi dat a register before the next character has been completely shifted in. otherwise, the first byte is lost. in spi slave mode, the control logic will sample the incoming si gnal of the sck pin. to ensure correct sampling of the clock signal, the minimum low and high periods should be: low period: longer than 2 cpu clock cycles. high period: longer than 2 cpu clock cycles. when the spi is enabled, the data dire ction of the mosi, miso, sck, and ss pins is overridden according to table 18-1 . for more details on automatic port overrides, refer to section 14.3 ?alternate port functions? on page 62 . table 18-1. spi pin overrides (1) pin direction, master spi direction, slave spi mosi user defined input miso input user defined sck user defined input ss user defined input note: 1. see section 14.3.2 ?alternate functions of port b? on page 65 for a detailed description of how to define the direction of the user defined spi pins. lsb slave msb 8 bit shift register lsb shift enable master msb ss sck ss sck mosi mosi miso miso 8 bit shift register spi clock generator 141 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 the following code examples show how to initialize the spi as a master and how to perform a simple transmission. ddr_spi in the examples must be replaced by the actual dat a direction register contro lling the spi pins. dd_mosi, dd_miso and dd_sck must be replaced by t he actual data direction bits for these pi ns. e.g. if mosi is placed on pin pb5, replace dd_mosi with ddb5 and ddr_spi with ddrb. note: 1. see section 4. ?about code examples? on page 8 . assembly code example (1) spi_masterinit: ; set mosi and sck output, all others input ldi r17,(1< atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 144 figure 18-4. spi transfer format with cpha = 1 18.5 register description 18.5.1 spcr ? spi control register ? bit 7 ? spie: spi interrupt enable this bit causes the spi interrupt to be executed if spif bit in the spsr register is set and the if the global interrupt enable bit in sreg is set. ? bit 6 ? spe: spi enable when the spe bit is written to one, the spi is enabled . this bit must be set to enable any spi operations. ? bit 5 ? dord: data order when the dord bit is written to one, the l sb of the data word is transmitted first. when the dord bit is written to zero, the msb of the data word is transmitted first. ? bit 4 ? mstr: master/slave select this bit selects master spi mode wh en written to one, and slave spi mode when written logic zero. if ss is configured as an input and is driven low while mstr is set, mstr will be clea red, and spif in spsr will become set. the user will then have to set mstr to re-enab le spi master mode. lsb msb bit 1 bit 6 bit 2 bit 5 bit 3 bit 4 bit 4 bit 3 bit 5 bit 2 bit 6 bit 1 msb lsb msb first (dord = 0) lsb first (dord =1) sck (cpol = 0) mode 1 sck (cpol = 1) mode 3 ss sample - mosi/miso change 0 mosi pin change 0 miso pin bit 76543210 0x2c (0x4c) spie spe dord mstr cpol cpha spr1 spr0 spcr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 145 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 ? bit 3 ? cpol: clock polarity when this bit is written to one, sck is high when idle. wh en cpol is written to zero, sck is low when idle. refer to figure 18-3 on page 143 and figure 18-4 on page 144 for an example. the cpol functionality is summarized below: ? bit 2 ? cpha: clock phase the settings of the clock phase bit (cpha) determine if data is sampled on the leading (first) or trailing (last) edge of sck. refer to figure 18-3 on page 143 and figure 18-4 on page 144 for an example. the cpol functionality is summarized below: ? bits 1:0 ? spr1, spr0: spi clock rate select 1 and 0 these two bits control the sck rate of the device configured as a master. spr1 and spr0 have no effect on the slave. the relationship between sck and the oscillator clock frequency f osc is shown in the following table: 18.5.2 spsr ? spi status register ? bit 7 ? spif: spi interrupt flag when a serial transfer is complete, the spif flag is set. an in terrupt is generated if spie in spcr is set and global interrupt s are enabled. if ss is an input and is driven low when the spi is in ma ster mode, this will also set the spif flag. spif is cleared by hardware when executing the corresponding interrupt handling vector. alternatively, the spif bit is cleared by first reading the spi status register with spif se t, then accessing the spi data register (spdr). table 18-3. cpol functionality cpol leading edge trailing edge 0 rising falling 1 falling rising table 18-4. cpha functionality cpha leading edge trailing edge 0 sample setup 1 setup sample table 18-5. relationship between sck and the oscillator frequency spi2x spr1 spr0 sck frequency 0 0 0 f osc / 4 0 0 1 f osc / 16 0 1 0 f osc / 64 0 1 1 f osc / 128 1 0 0 f osc / 2 1 0 1 f osc / 8 1 1 0 f osc / 32 1 1 1 f osc / 64 bit 76543210 0x2d (0x4d) spif wcol ? ? ? ? ? spi2x spsr read/write rrrrrrrr/w initial value00000000 atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 146 ? bit 6 ? wcol: write collision flag the wcol bit is set if the spi data register (spdr) is writte n during a data transfer. the wcol bit (and the spif bit) are cleared by first reading the spi stat us register with wcol set, and then accessing the spi data register. ? bit 5:1 ? reserved these bits are reserved and will always read as zero. ? bit 0 ? spi2x: double spi speed bit when this bit is written logic one the spi speed (sck fr equency) will be doubled when the spi is in master mode (see table 18-5 on page 145 ). this means that the minimum sck period w ill be two cpu clock periods. when the spi is configured as slave, the spi is only guaranteed to work at f osc /4 or lower. the spi interface on the atmega164p-b/32 4p-b/644p-b is also used for program memory and eeprom downloading or uploading. see section 27.8 ?serial downloading? on page 270 for serial programming and verification. 18.5.3 spdr ? spi data register the spi data register is a read/ write register used for data transfer between the register file and the spi shift register. writing to the register initiates data tr ansmission. reading the register causes the shift register receive buffer to be read. bit 76543210 0x2e (0x4e) msb lsb spdr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial valuexxxxxxxxu ndefined 147 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 19. usart 19.1 features full duplex operation (independent serial receive and transmit registers) asynchronous or synchronous operation master or slave clocked synchronous operation high resolution baud rate generator supports serial frames with 5, 6, 7, 8, or 9 data bits and 1 or 2 stop bits odd or even parity generation and parity check supported by hardware data overrun detection framing error detection noise filtering includes false start bit detection and digital low pass filter three separate interrupts on tx complete, tx data register empty and rx complete multi-processor communication mode double speed asynchronous communication mode 19.2 usart1 and usart0 the atmega164p-b/324p-b/644p-b has two usart?s, usart0 and usart1. the functionality for all usart?s is described below, most regist er and bit references in this section are written in general form. a lower case ?n? replaces the usart number. usart0 and usart1 have different i/o registers as shown in section 30. ?register summary? on page 323 . 19.3 overview the universal synchronous and asynchronous serial receiver and transmitter (usart) is a highly flexible serial communication device. a simplified block diagram of the usart transmitter is shown in figure 19-1 on page 148 . cpu accessible i/o registers and i/o pins are shown in bold. the power reducion usart0 bit, prusart0, in section 10.12.3 ?prr0 ? power re duction register 0? on page 39 must be disabled by writing a logical zero to it. the power reducion usart1 bit, prusart1, in section 10.12.4 ?prr1 ? power re duction register 1? on page 39 must be disabled by writing a logical zero to it. atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 148 figure 19-1. usart block diagram (1) note: 1. see figure 1-1 on page 3 and section 14.3 ?alternate port functions? on page 62 for usart pin placement. the dashed boxes in the block diagram separate the three main parts of the usart (listed fr om the top): clock generator, transmitter and receiver. control register s are shared by all units. the clock gener ation logic consists of synchronization logic for external clock input used by synchronous slave opera tion, and the baud rate generator. the xckn (transfer clock) pin is only used by synchronous transfer m ode. the transmitter consists of a single write buffer, a serial shift register, pari ty generator and control logic for handling diff erent serial frame formats. the write buffer allows a continuous transfer of data without any delay between frames. the receiv er is the most complex part of the usart module due to its clock and data recovery units. the recovery units are used for asynchronous data reception. in addition to the recovery units, the receiver includes a parity checker, control logic, a shift register and a two level receive buffer (udrn). the receiver supports the same frame formats as the transmitter, and can de tect frame error, data overrun and parity errors. transmit shift register receive shift register data recoverc clock recoverc parity checker parity generator pin control tx control pin control pin control rx control udr (transmit) transmitter clock generator receiver ucsra ucsrc ucsrb sync logic osc udr (receive) data bus baud rate generator ubrr[h:l] xck rxd txd 149 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 19.4 clock generation the clock generation logic generates the base clock for the transmitter and receiver. the usartn supports four modes of clock operation: normal asynchronous, double speed asynchro nous, master synchronous and slave synchronous mode. the umseln bit in usart control and st atus register c (ucsrnc) selects between asynchronous and synchronous operation. double speed (asynchronous mo de only) is controlled by the u2xn fo und in the ucsrna register. when using synchronous mode (umseln = 1), the data direction register for the xckn pin (ddr_xckn) controls whether the clock source is internal (master mode) or external (slave mode) . the xckn pin is only active when using synchronous mode. figure 19-2 shows a block diagram of the clock generation logic. figure 19-2. clock generati on logic, block diagram signal description: txclk transmitter clock (internal signal). rxclk receiver base clock (internal signal). xcki input from xck pin (internal signal). used for synchronous slave operation. xcko clock output to xck pin (internal signal ). used for synchronous master operation. f osc xtal pin frequency (system clock). 19.4.1 internal clock generation ? the baud rate generator internal clock generation is used for the asynchronous and the synchronous master modes of operation. the description in this section refers to figure 19-2 . the usart baud rate register (ubrrn) a nd the down-counter connect ed to it function as a programmable prescaler or baud rate generator. the down-counter, running at system clock (f osc ), is loaded with the ubrrn value each time the counter has counted down to zero or when the ubrrnl register is written. a clock is generated each time the counter reaches zero. this clock is the baud rate generator clock output (= f osc /(ubrrn+1)). the transmitter divides the baud rate generator clock output by 2, 8 or 16 depending on mode. the baud rate generator output is used directly by the receiver?s clock and data recovery units. however, the recovery units us e a state machine that uses 2, 8 or 16 states depending on mode set by the state of the um seln, u2xn and ddr_xckn bits. sync register edge detector prescaling down-counter /2 xck pin /4 0 0 1 1 0 1 0 1 /2 ubrr ddr_xck ucpol u2x ddr_xck ubrr+1 txclk rxclk umsel fosc osc xcki xcko atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 150 table 19-1 contains equations for calculating the baud rate (in bits per second) and for calculating the ubrrn value for each mode of operation using an internally generated clock source. some examples of ubrrn values for some system clock frequencies are found in table 19-9 on page 167 . 19.4.2 double speed operation (u2xn) the transfer rate can be doubled by setting the u2xn bit in ucsrna. setting this bit only has effect for the asynchronous operation. set this bit to zero when using synchronous operation. setting this bit will reduce the divisor of the baud rate divi der from 16 to 8, effectively doubling the transfer rate for asynchronous communication. note however that the receiver will in this case only use half the number of samples (reduced from 16 to 8) for data sampling and clock recovery, and ther efore a more accurate baud rate setting and system clock are required when this mode is used. for the transmitter, there are no downsides. 19.4.3 external clock external clocking is used by the synchronous slave modes of operation. the description in this section refers to figure 19-2 on page 149 for details. external clock input from the xckn pin is sampled by a synchro nization register to minimize the chance of meta-stability. the output from the synchronization regi ster must then pass through an edge de tector before it can be used by the transmitter and receiver. this process introduces a two cpu clock period delay and therefore the maximum external xckn clock frequency is limited by the following equation: note that f osc depends on the stability of the system clock source. it is therefore recommended to add some margin to avoid possible loss of data due to frequency variations. table 19-1. equations for calculat ing baud rate register setting operating mode equation for calculating baud rate (1) equation for calculating ubrr value asynchronous normal mode (u2xn = 0) asynchronous double speed mode (u2xn = 1) synchronous master mode notes: 1. the baud rate is defined to be the transfer rate in bit per second (bps) 2. baud - baud rate (in bits per second, bps) 3. f osc - system oscillator clock frequency 4. ubrrn - contents of the ubrrnh and ubrrnl registers, (0-4095) baud f osc 16 ubrrn 1 + () --------------------------------------------- = ubrrn f osc 16baud ---------------------- - 1 ? = baud f osc 8 ubrrn 1 + () ------------------------------------------ = ubrrn f osc 8baud ------------------- - 1 ? = baud f osc 2 ubrrn 1 + () ------------------------------------------ = ubrrn f osc 2baud ------------------- - 1 ? = f xck f osc 4 ----------- < 151 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 19.4.4 synchronous clock operation when synchronous mode is used (umseln = 1), the xckn pin will be used as either clock input (slave) or clock output (master). the dependency between the clock edges and data sa mpling or data change is the same. the basic principle is that data input (on rxdn) is sampled at the opposite xckn clock edge of the edge the data output (txdn) is changed. figure 19-3. synchronous mode xckn timing the ucpoln bit ucrsc selects which xckn clock edge is used for data sampling and which is used for data change. as figure 19-3 shows, when ucpoln is zero the data will be changed at rising xckn edge and sampled at falling xckn edge. if ucpoln is set, the data will be changed at falling xckn edge and sampled at rising xckn edge. 19.5 frame formats a serial frame is defined to be one character of data bits with synchronization bits (start and stop bits), and optionally a pa rity bit for error checking. the usart accepts all 30 comb inations of the following as valid frame formats: 1 start bit 5, 6, 7, 8, or 9 data bits no, even or odd parity bit 1 or 2 stop bits a frame starts with the start bit followed by the least signific ant data bit. then the next data bits, up to a total of nine, a re succeeding, ending with the most significant bit. if enabled, the parity bit is insert ed after the data bits, before the stop b its. when a complete frame is transmitted, it can be directly follow ed by a new frame, or the communication line can be set to an idle (high) state. figure 19-4 illustrates the possible combinations of the fr ame formats. bits inside brackets are optional. figure 19-4. frame formats st start bit, always low. (n) data bits (0 to 8). p parity bit. can be odd or even. sp stop bit, always high. idle no transfers on the communication line (rxdn or txdn). an idle line must be high. the frame format used by the usart is set by the ucszn 2:0, upmn1:0 and usbsn bits in ucsrnb and ucsrnc. the receiver and transmitter use the same setting. note that c hanging the setting of any of thes e bits will corrupt all ongoing communication for both the receiver and transmitter. xck rxd/ txd xck ucpol = 1 ucpol = 0 rxd/ txd sample sample st 0 1 2 3 4 [5] [6] [7] [8] (st/ idle) (idle) frame [p] sp1 [sp2] atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 152 the usart character size (ucszn2:0) bits select the number of data bits in the frame. the usart parity mode (upmn1:0) bits enable and set the type of parity bit. the selection between one or two stop bits is done by the usart stop bit select (usbsn) bit. the receiver ignores the second stop bit. an fe (f rame error) will therefore only be detected in the cases where the first stop bit is zero. 19.5.1 parity bit calculation the parity bit is calculated by doing an exclusive-or of all the data bits. if odd parity is used, the result of the exclusive or is inverted. the relation between the parity bit and data bits is as follows: p even parity bit using even parity p odd parity bit using odd parity d n data bit n of the character if used, the parity bit is located between the last data bit and first stop bit of a serial frame. 19.6 usart initialization the usart has to be initialized before any communication can take place. the initialization process normally consists of setting the baud rate, setting frame format and enabling the tran smitter or the receiver depending on the usage. for interrupt driven usart operation, the global interrupt flag should be cleared and the usart interrupts should be disabled. before doing a re-initialization with changed baud rate or fr ame format, be sure that there are no ongoing transmissions during the period the registers are changed. the txcn flag c an be used to check that the transmitter has completed all transfers, and the rxc flag can be used to check that there are no unread data in the receive buffer. note that the txcn flag must be cleared before each transmission (before ud rn is written) if it is used for this purpose. the following simple usart initialization code examples sh ow one assembly and one c function that are equal in functionality. the examples assume asyn chronous operation using polling (no interr upts enabled) and a fixed frame format. the baud rate is given as a function parameter. for the assembly code, the baud rate parameter is assumed to be stored in the r17:r16 registers. note: 1. see section 4. ?about code examples? on page 8 . p even d n 1 ? d 3 d 2 d 1 d 0 0 p odd d n 1 ? d 3 d 2 d 1 d 0 1 = = assembly code example (1) usart_init: ; set baud rate out ubrrnh, r17 out ubrrnl, r16 ; enable receiver and transmitter ldi r16, (1< atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 156 the following code example shows a simple usart receive func tion based on polling of the receive complete (rxcn) flag. when using frames with less than eight bits the most signific ant bits of the data read from the udrn will be masked to zero. the usart has to be initialized before the function can be used. note: 1. see section 4. ?about code examples? on page 8 . the function simply waits for data to be present in the rece ive buffer by checking the rxcn flag, before read ing the buffer and returning the value. 19.8.2 receiving frames with 9 data bits if 9-bit characters are used (ucszn=7) the ninth bit must be read from the rxb8n bit in ucsrnb before reading the low bits from the udrn. this rule applies to the fen, dorn and upen st atus flags as well. read stat us from ucsrna, then data from udrn. reading the udrn i/o location will change the stat e of the receive buffer fifo and consequently the txb8n, fen, dorn and upen bits, which all are stored in the fifo, will change. the following code example shows a simple usart receive func tion that handles both nine bit characters and the status bits. assembly code example (1) usart_receive: ; wait for data to be received sbis ucsrna, rxcn rjmp usart_receive ; get and return received data from buffer in r16, udrn ret c code example (1) unsigned char usart_receive( void ) { /* wait for data to be received */ while (!(ucsrna & (1< atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 158 19.8.3 receive compete flag and interrupt the usart receiver has one flag th at indicates the receiver state. the receive complete (rxcn) flag indicates if there are unrea d data present in the receive buf fer. this flag is one when unread data exist in the receive buffer, and zero when the receiv e buffer is empty (i.e., does no t contain any unread data). if the receiver is disabled (rxenn = 0), the receive buffer will be flushed and consequently the rxcn bit will become zero. when the receive complete interrupt enable (rxcien) in ucsrnb is set, the usart receive complete interrupt will be executed as long as the rxcn flag is set (provided that global interrupts are en abled). when interrupt-driven data reception is used, the receive complete routine must read the received da ta from udrn in order to clear the rxcn flag, otherwise a new interrupt will occur once the interrupt routine terminates. 19.8.4 receiver error flags the usart receiver has three error flags: frame error (fen ), data overrun (dorn) and parity error (upen). all can be accessed by reading ucsrna. common for the error flags is that they are located in the receive buffer together with the frame for which they indicate the error status. due to the buff ering of the error flags, the ucsrna must be read before the receive buffer (udrn), since reading the udrn i/o location changes the buffer read location. another equality for the error flags is that they can not be altered by so ftware doing a write to the flag location. ho wever, all flags must be set to zero wh en the ucsrna is written for upward compatibility of future u sart implementations. none of the error flags can generate interrupts. the frame error (fen) flag indicates the state of the first stop bit of the next readable frame st ored in the receive buffer. t he fen flag is zero when the stop bit was correctly read (as one), and the fen flag will be one when the stop bit was incorrect (zero). this flag can be used for detectin g out-of-sync conditions, detecting break conditions and protocol handling. the fen flag is not affected by the setting of the usbsn bit in ucsrnc si nce the receiver ignores all, e xcept for the first, stop bits. for compatibility with future de vices, always set this bit to zero when writing to ucsrna. the data overrun (dorn) flag indicates data loss due to a re ceiver buffer full condition. a data overrun occurs when the receive buffer is full (two characters), it is a new character waiting in the receiv e shift register, and a new start bit is de tected. if the dorn flag is set there was one or more serial frame lost between the frame last r ead from udrn, and the next frame read from udrn. for compatibility with future devices, always writ e this bit to zero when writing to ucsrna. the dorn flag is cleared when the frame received was successfully mo ved from the shift register to the receive buffer. the parity error (upen) flag indicates that the next frame in the receive buffer had a parity error when received. if parity check is not enabled the upen bit will always be read zero. for compatibility with future devices, always set this bit to zero when writing to ucsrna. for more details see section 19.5.1 ?parity bit calculation? on page 152 and section 19.8.5 ?parity checker? on page 158 . 19.8.5 parity checker the parity checker is active when the high usart parity mode (u pmn1) bit is set. type of parit y check to be performed (odd or even) is selected by the upmn0 bit. when enabled, the parity checker calculates the parity of the data bits in incoming frames and compares the result with the pari ty bit from the serial frame. the result of the check is stored in the receive buff er together with the received data and stop bits . the parity error (upen) flag can then be read by software to check if the frame had a parity error. the upen bit is set if the next character that can be read from the receive buffer had a parity error when received and the parity checking was enabled at that point (upmn1 = 1). this bit is valid until the receive buffer (udrn) is read. 19.8.6 disabling the receiver in contrast to the transmitter, disabling of the receiver will be immediate. data from ongoing receptions will therefore be los t. when disabled (i.e., the rxenn is set to ze ro) the receiver will no longer override th e normal function of the rxdn port pin. the receiver buffer fifo will be flushed when the receiver is disabled. remaining data in the buffer will be lost 159 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 19.8.7 flushing the receive buffer the receiver buffer fifo will be flushed wh en the receiver is disabled , i.e., the buffer will be empt ied of its contents. unrea d data will be lost. if the buffer has to be flushed during normal operation, due to for instance an error condition, read the ud rn i/o location until the rxcn flag is cleared. the following code example shows how to flush the receive buffer. note: 1. see section 4. ?about code examples? on page 8 . 19.9 asynchronous data reception the usart includes a clock recovery and a data recovery unit for handling asynchronous data reception. the clock recovery logic is used for synchronizing the internally generated baud rate clock to the incoming asynchronous serial frames at the rxdn pin. the data recovery logic samples and low pass filters each incoming bit, thereby improving the noise immunity of the receiver. the asynchronous reception operati onal range depends on the accuracy of the internal baud rate clock, the rate of the incoming frames, and the frame size in number of bits. 19.9.1 asynchronous clock recovery the clock recovery logic synch ronizes internal cl ock to the incoming serial frames. figure 19-5 illustrates the sampling process of the start bit of an incoming frame. the sample rate is 16 times the baud rate for normal mode, and eight times the baud rate for double speed mode. the horizontal arrows illustra te the synchronization variation due to the sampling process. note the larger time variation when using the double spee d mode (u2xn = 1) of operation. samples denoted zero are samples done when the rxdn line is idle (i.e., no communication activity). figure 19-5. start bit sampling when the clock recovery logic detects a high (idle) to low (sta rt) transition on the rxdn line, the start bit detection sequenc e is initiated. let sample 1 denote the first zero-sample as shown in the figure. the clock recovery logic then uses samples 8, 9, and 10 for normal mode, and samples 4, 5, and 6 for double speed mode (indicated with sample numbers inside boxes on the figure), to decide if a valid start bi t is received. if two or more of these th ree samples have logical high levels (the ma jority wins), the start bit is rejected as a noise spike and the receiver starts looking for the next high to low-transition. if howev er, a valid start bit is detected, t he clock recovery logic is synchronized and the data recovery can begin. the synchronization process is repeated for each start bit. assembly code example (1) usart_flush: sbis ucsrna, rxcn ret in r16, udrn rjmp usart_flush c code example (1) void usart_flush( void ) { unsigned char dummy; while (ucsrna & (1< 161 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 19.9.3 asynchronous operational range the operational range of the receiver is dependent on the mismatch between th e received bit rate and the internally generated baud rate. if the transmitter is sendi ng frames at too fast or too slow bit rates, or the internally generated baud r ate of the receiver does not have a similar (see table 19-2 on page 161 ) base frequency, the receiver will not be able to synchronize the frames to the start bit. the following equations can be used to calculate the ratio of the incoming data rate and internal receiver baud rate. d sum of character size and parity size (d = 5 to 10 bit) s samples per bit. s = 16 for normal speed mode and s = 8 for double speed mode. s f first sample number used for majority voting. s f = 8 for normal speed and s f = 4 for double speed mode. s m middle sample number used for majority voting. s m = 9 for normal speed and s m = 5 for double speed mode. r slow is the ratio of the slowest incoming data rate that can be accepted in relation to the receiver baud rate. r fast is the ratio of the fastest incoming data rate that can be accepted in relation to the receiver baud rate. table 19-2 and table 19-3 list the maximum receiver baud rate error that c an be tolerated. note t hat normal speed mode has higher toleration of baud rate variations. table 19-2. recommended maximum receiver baud rate error for normal speed mode (u2xn = 0) d# (data+parity bit) r slow (%) r fast (%) max total error (%) recommended max receiver error (%) 5 93.20 106.67 +6.67/?6.8 3.0 6 94.12 105.79 +5.79/?5.88 2.5 7 94.81 105.11 +5.11/?5.19 2.0 8 95.36 104.58 +4.58/?4.54 2.0 9 95.81 104.14 +4.14/?4.19 1.5 10 96.17 103.78 +3.78/?3.83 1.5 table 19-3. recommended maximum receiver baud rate error for double speed mode (u2xn = 1) d# (data+parity bit) r slow (%) r fast (%) max total error (%) recommended max receiver error (%) 5 94.12 105.66 +5.66/?5.88 2.5 6 94.92 104.92 +4.92/?5.08 2.0 7 95.52 104,35 +4.35/?4.48 1.5 8 96.00 103.90 +3.90/?4.00 1.5 9 96.39 103.53 +3.53/?3.61 1.5 10 96.70 103.23 +3.23/?3.30 1.0 r slow d1 + () s s1 ? d + ss f + -------------------------------------------- - = r fast d2 + () s d1 + () ss m + ----------------------------------------- - = atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 162 the recommendations of the maximum receiver baud rate e rror was made under the assumption that the receiver and transmitter equally divides the maximum total error. there are two possible sources for the receivers baud rate erro r. the receiver?s system clo ck (xtal) will always have some minor instability over the supply voltage range and the temper ature range. when using a cryst al to generate the system clock, this is rarely a problem, but for a resonator the syst em clock may differ more than 2% depending of the resonators tolerance. the second source for the error is more controllable. the baud rate generator can not always do an exact division of the system frequency to get t he baud rate wanted. in this case an ubrr value that gives an accept able low error can be used if possible. 19.10 multi-processor communication mode setting the multi-processor communication mode (mpcmn) bit in ucsrna enables a filtering function of incoming frames received by the usart receiver. frames that do not contain address information will be ignored and not put into the receive buffer. this effectively reduces the number of incoming frames that has to be handled by the cpu, in a system with multiple mcus that communicate via the same serial bus. the transmitter is unaffected by the mpcmn setting, but has to be used differently when it is a part of a system ut ilizing the multi-proces sor communication mode. if the receiver is set up to receive fram es that contain 5 to 8 data bits, then the first stop bit indicates if the frame conta ins data or address information. if the receiver is set up for frames with nine data bits, then the ninth bit (rxb8n) is used for identifying address and data frames. when the frame type bit (the first stop or the ninth bit) is one, the frame contains an address. when the frame type bit is zero the frame is a data frame. the multi-processor communication mode enables several slave m cus to receive data from a ma ster mcu. this is done by first decoding an address frame to find out which mcu has be en addressed. if a particular slave mcu has been addressed, it will receive the following data frames as normal, while the other slave mcus will ignore the received frames until another address frame is received. 19.10.1 using mpcmn for an mcu to act as a master mcu, it can use a 9-bit character frame format (ucszn = 7). the ninth bit (txb8n) must be set when an address frame (txb8n = 1) or cleared when a data fr ame (txb = 0) is being transmitted. the slave mcus must in this case be set to use a 9-bit character frame format. the following procedure should be used to exchange data in multi-processor communication mode: 1. all slave mcus are in multi-processor comm unication mode (mpcmn in ucsrna is set). 2. the master mcu sends an address frame, and all slaves receive and read this frame. in the slave mcus, the rxcn flag in ucsrna will be set as normal. 3. each slave mcu reads the udrn register and determines if it has been selected. if so, it clears the mpcmn bit in ucsrna, otherwise it waits for the next addr ess byte and keeps the mpcmn setting. 4. the addressed mcu will receive all data frames until a new address frame is received. the other slave mcus, which still have the mpcmn bit set, will ignore the data frames. 5. when the last data frame is received by the addre ssed mcu, the addressed mcu sets the mpcmn bit and waits for a new address frame from master. the process then repeats from 2. using any of the 5- to 8-bit character frame formats is possi ble, but impractical since the receiver must change between using n and n+1 character frame formats. this makes full-duplex operation difficult since the transmitter and receiver uses the same character size setting. if 5- to 8-bit character fr ames are used, the transmitter mu st be set to use two stop bit (usbsn = 1) since the firs t stop bit is used for indicating the frame type. do not use read-modify-write instructions (sbi and cbi) to se t or clear the mpcmn bit. the mpcmn bit shares the same i/o location as the txcn flag and this might accidental ly be cleared when using sbi or cbi instructions. 163 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 19.11 register description 19.11.1 udrn ? usart i/o data register n the usart transmit data buffer register an d usart receive data buffer registers share the same i/o address referred to as usart data register or udrn. the transmit data buffer regist er (txb) will be the destination for data written to the udrn register location. reading the udrn register location will return the contents of the receive data buffer register (rxb). for 5-, 6-, or 7-bit characters the upper unused bits will be ignored by the transmitter and set to zero by the receiver. the transmit buffer can only be written when the udren flag in the ucsrna regist er is set. data written to udrn when the udren flag is not set, will be ignored by the usart transmit ter. when data is written to the transmit buffer, and the transmitter is enabled, the transmitter will load the data into th e transmit shift register when th e shift register is empty. t hen the data will be serially transmitted on the txdn pin. the receive buffer consists of a two level fifo. the fifo will change its state whenever the re ceive buffer is accessed. due to this behavior of the receive buffer, do not use read-modify-write instructions (sbi and cbi) on this location. be careful when using bit test instructions (sbic and sbis), since these also will change the state of the fifo. 19.11.2 ucsrna ? usart control and status register a ? bit 7 ? rxcn: usart receive complete this flag bit is set when there are unread data in the rece ive buffer and cleared when the receive buffer is empty (i.e., does not contain any unread data). if the receiver is disabled, the receive buffer will be flushed and consequently the rxcn bit wil l become zero. the rxcn flag can be used to generate a receiv e complete interrupt (see description of the rxcien bit). ? bit 6 ? txcn: usart transmit complete this flag bit is set when the entire frame in the transmit shi ft register has been shifted out and there are no new data curren tly present in the transmit buffer (udrn). th e txcn flag bit is automatically cleared when a transmit complete interrupt is executed, or it can be cleared by writin g a one to its bit location. the txcn flag c an generate a transmit complete interrupt (see description of the txcien bit). ? bit 5 ? udren: usart data register empty the udren flag indicates if the transmit buffer (udrn) is ready to receive new data. if udren is one, the buffer is empty, and therefore ready to be written. the udren flag can generat e a data register empty interrupt (see description of the udrien bit).udren is set after a reset to indicate that the transmitter is ready. ? bit 4 ? fen: frame error this bit is set if the next character in the receive buffer had a frame error when received. i.e. , when the first stop bit of t he next character in the receive buffer is zero . this bit is valid until the receive buff er (udrn) is read. the fen bit is zero wh en the stop bit of received data is one. alwa ys set this bit to zero when writing to ucsrna. ? bit 3 ? dorn: data overrun this bit is set if a data overrun condition is detected. a data overrun occurs when the receive buffer is full (two characters) , it is a new character waiting in the receive shift register, and a new start bit is detected. this bit is valid until the receive buffer (udrn) is read. always set this bit to zero when writing to ucsrna. bit 76543210 rxb[7:0] udrn (read) txb[7:0] udrn (write) read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 rxcn txcn udren fen dorn upen u2xn mpcmn ucsrna read/write r r/w r r r r r/w r/w initial value00100000 atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 164 ? bit 2 ? upen: usart parity error this bit is set if the next character in the receive buffer had a parity error when received and the parity checking was enable d at that point (upmn1 = 1). this bit is valid until the receive bu ffer (udrn) is read. always set this bit to zero when writing to ucsrna. ? bit 1 ? u2xn: double the usart transmission speed this bit only has effect for the asyn chronous operation. write this bit to zero when using synchronous operation. writing this bit to one will reduce the divisor of the baud rate di vider from 16 to 8 effectively doubling the transfer rate fo r asynchronous communication. ? bit 0 ? mpcmn: multi-processor communication mode this bit enables the multi-processor communication mode. when the mpcmn bit is written to one, all the incoming frames received by the usart receiver that do not contain address information will be ignored. the tr ansmitter is unaffected by the mpcmn setting. for more detailed information see section 19.10 ?multi-processor communication mode? on page 162 . 19.11.3 ucsrnb ? usart control and status register n b ? bit 7 ? rxcien: rx complete interrupt enable n writing this bit to one enables interrupt on the rxcn flag. a usart receive complete interrupt will be generated only if the rxcien bit is written to one, the global interrupt flag in sreg is written to one and the rxcn bit in ucsrna is set. ? bit 6 ? txcien: tx complete interrupt enable n writing this bit to one enables interrupt on the txcn flag. a u sart transmit complete interrupt will be generated only if the txcien bit is written to one, the global interrupt flag in sreg is written to one and the txcn bit in ucsrna is set. ? bit 5 ? udrien: usart data regi ster empty interrupt enable n writing this bit to one enables interrupt on the udren flag. a data register empty interrupt will be generated only if the udrien bit is written to one, the global interrupt flag in sreg is written to one and the udren bit in ucsrna is set. ? bit 4 ? rxenn: receiver enable n writing this bit to one enables the usart receiver. the receiv er will override normal port operation for the rxdn pin when enabled. disabling the receiver will flush the receiv e buffer invalidating the fen, dorn, and upen flags. ? bit 3 ? txenn: transmitter enable n writing this bit to one enables the usart transmitter. the tr ansmitter will override normal port operation for the txdn pin when enabled. the disabling of the transmitter (writing txenn to zero) will not become effective until ongoing and pending transmissions are completed, i.e., when the transmit shift regi ster and transmit buffer register do not contain data to be transmitted. when disabled, the transmitter will no longer override the txdn port. ? bit 2 ? ucszn2: character size n the ucszn2 bits combined with the ucszn1:0 bit in ucsrnc se ts the number of data bits (cha racter size) in a frame the receiver and transmitter use. ? bit 1 ? rxb8n: receive data bit 8 n rxb8n is the ninth data bit of the received character when ope rating with serial frames with nine data bits. must be read before reading the low bits from udrn. bit 76543210 rxcien txcien udrien rxenn txenn ucszn2 rxb8n txb8n ucsrnb read/write r/w r/w r/w r/w r/w r/w r r/w initial value 0 0 0 0 0 0 0 0 165 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 ? bit 0 ? txb8n: transmit data bit 8 n txb8n is the ninth data bit in the characte r to be transmitted when operating with seri al frames with nine data bits. must be written before writing the low bits to udrn. 19.11.4 ucsrnc ? usart control and status register n c ? bits 7:6 ? umseln1:0 usart mode select these bits select the mode of oper ation of the usartn as shown in table 19-4 . ? bits 5:4 ? upmn1:0: parity mode these bits enable and set type of parity generation and c heck. if enabled, the transmitter will automatically generate and send the parity of the transmit ted data bits within each frame. the receiver will generate a parity value for the incoming data and compare it to the upmn setting. if a mismatch is detected, the upen flag in ucsrna will be set. ? bit 3 ? usbsn: stop bit select this bit selects the number of stop bits to be inserted by the transmitter. the receiver ignores this setting. ? bit 2:1 ? ucszn1:0: character size the ucszn1:0 bits combined with the ucszn2 bit in ucsrnb sets the number of data bits (character size) in a frame the receiver and transmitter use. bit 7 6 543 2 1 0 umseln1 umseln0 upmn1 upmn0 usbsn ucszn1 ucszn0 ucpoln ucsrnc read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 1 1 0 table 19-4. umseln bits settings umseln1 umseln0 mode 0 0 asynchronous usart 0 1 synchronous usart 1 0 (reserved) 1 1 master spi (mspim) (1) note: 1. see section 20. ?usart in spi mode? on page 169 for full description of the master spi mode (mspim) operation. table 19-5. upmn bits settings upmn1 upmn0 parity mode 0 0 disabled 0 1 reserved 1 0 enabled, even parity 1 1 enabled, odd parity table 19-6. usbs bit settings usbsn stop bit(s) 0 1-bit 1 2-bit atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 166 ? bit 0 ? ucpoln: clock polarity this bit is used for synchronous mode only. write this bit to zero when asynchronous mode is used. the ucpoln bit sets the relationship between data output change and data input sample, and the synchronous clock (xckn). 19.11.5 ubrrnl and ubrrnh ? usart baud rate registers ? bit 15:12 ? reserved these bits are reserved for future use. for compatibility with future devices, these bit must be written to zero when ubrrh is written. ? bit 11:0 ? ubrr11:0: usart baud rate register this is a 12-bit register which contai ns the usart baud rate. the ubrrh contains the four most significant bits, and the ubrrl contains the eight least significant bits of the u sart baud rate. ongoing transmissi ons by the transmitter and receiver will be corrupted if the baud rate is changed. writ ing ubrrl will trigger an immediate update of the baud rate prescaler. 19.12 examples of baud rate setting for standard crystal and resonator freque ncies, the most commonly used baud ra tes for asynchronous operation can be generated by using the ubrr settings in table 19-9 on page 167 to table 19-12 on page 168 . ubrr values which yield an actual baud rate differing less than 0.5% from the target baud rate, are bold in the table. higher error ratings are acceptable , but the receiver will have less noise resistance when the erro r ratings are high, especially for large serial frames (see section 19.9.3 ?asynchronous operational range? on page 161 ). the error values are calculated using the following equation: table 19-7. ucszn bits settings ucszn2 ucszn1 ucszn0 character size 0 0 0 5-bit 0 0 1 6-bit 0 1 0 7-bit 0 1 1 8-bit 1 0 0 reserved 1 0 1 reserved 1 1 0 reserved 1 1 1 9-bit table 19-8. ucpoln bit settings ucpoln transmitted data changed (output of txdn pin) received data sampled (input on rxdn pin) 0 rising xckn edge falling xckn edge 1 falling xckn edge rising xckn edge bit 151413121110 9 8 ? ? ? ? ubrr[11:8] ubrrnh ubrr[7:0] ubrrnl 76543210 read/write rrrrr/wr/wr/wr/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 00000000 00000000 error[%] baudrate closest match baudrate -------------------------------------------------- 1 ? ?? ?? 100% ? = 167 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 table 19-9. examples of ubrrn settings for co mmonly used oscillator frequencies baud rate (bps) f osc = 1.0000mhz f osc = 1.8432mhz f osc = 2.0000mhz u2xn = 0 u2xn = 1 u2xn = 0 u2xn = 1 u2xn = 0 u2xn = 1 ubrr error ubrr error ubrr error ubrr error ubrr error ubrr error 2400 25 0.2% 51 0.2% 47 0.0% 95 0.0% 51 0.2% 103 0.2% 4800 12 0.2% 25 0.2% 23 0.0% 47 0.0% 25 0.2% 51 0.2% 9600 6 ?7.0% 12 0.2% 11 0.0% 23 0.0% 12 0.2% 25 0.2% 14.4k 3 8.5% 8 ?3.5% 7 0.0% 15 0.0% 8 ?3.5% 16 2.1% 19.2k 2 8.5% 6 ?7.0% 5 0.0% 11 0.0% 6 ?7.0% 12 0.2% 28.8k 1 8.5% 3 8.5% 3 0.0% 7 0.0% 3 8.5% 8 ?3.5% 38.4k 1 ?18.6% 2 8.5% 2 0.0% 5 0.0% 2 8.5% 6 ?7.0% 57.6k 0 8.5% 1 8.5% 1 0.0% 3 0.0% 1 8.5% 3 8.5% 76.8k ? ? 1 ?18.6% 1 ?25.0% 2 0.0% 1 ?18.6% 2 8.5% 115.2k ? ? 0 8.5% 0 0.0% 1 0.0% 0 8.5% 1 8.5% 230.4k ? ? ? ? ? ? 0 0.0% ? ? ? ? 250k ? ? ? ? ? ? ? ? ? ? 0 0.0% max. (1) 62.5kbps 125kbps 115.2kbps 230.4kbps 125kbps 250kbps note: 1. ubrr = 0, error = 0.0% table 19-10. examples of ubrrn setti ngs for commonly used oscill ator frequencies (continued) baud rate (bps) f osc = 3.6864mhz f osc = 4.0000mhz f osc = 7.3728mhz u2xn = 0 u2xn = 1 u2xn = 0 u2xn = 1 u2xn = 0 u2xn = 1 ubrr error ubrr error ubrr error ubrr error ubrr error ubrr error 2400 95 0.0% 191 0.0% 103 0.2% 207 0.2% 191 0.0% 383 0.0% 4800 47 0.0% 95 0.0% 51 0.2% 103 0.2% 95 0.0% 191 0.0% 9600 23 0.0% 47 0.0% 25 0.2% 51 0.2% 47 0.0% 95 0.0% 14.4k 15 0.0% 31 0.0% 16 2.1% 34 ?0.8% 31 0.0% 63 0.0% 19.2k 11 0.0% 23 0.0% 12 0.2% 25 0.2% 23 0.0% 47 0.0% 28.8k 7 0.0% 15 0.0% 8 ?3.5% 16 2.1% 15 0.0% 31 0.0% 38.4k 5 0.0% 11 0.0% 6 ?7.0% 12 0.2% 11 0.0% 23 0.0% 57.6k 3 0.0% 7 0.0% 3 8.5% 8 ?3.5% 7 0.0% 15 0.0% 76.8k 2 0.0% 5 0.0% 2 8.5% 6 ?7.0% 5 0.0% 11 0.0% 115.2k 1 0.0% 3 0.0% 1 8.5% 3 8.5% 3 0.0% 7 0.0% 230.4k 0 0.0% 1 0.0% 0 8.5% 1 8.5% 1 0.0% 3 0.0% 250k 0 ?7.8% 1 ?7.8% 0 0.0% 1 0.0% 1 ?7.8% 3 ?7.8% 0.5m ? ? 0 ?7.8% ? ? 0 0.0% 0 ?7.8% 1 ?7.8% 1m ? ? ? ? ? ? ? ? ? ? 0 ?7.8% max. (1) 230.4kbps 460.8kbps 250kbps 0.5mbps 460.8kbps 921.6kbps note: 1. ubrr = 0, error = 0.0% atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 168 table 19-11. examples of ubrrn setti ngs for commonly used oscill ator frequencies (continued) baud rate (bps) f osc = 8.0000mhz f osc = 11.0592mhz f osc = 14.7456mhz u2xn = 0 u2xn = 1 u2xn = 0 u2xn = 1 u2xn = 0 u2xn = 1 ubrr error ubrr error ubrr error ubrr error ubrr error ubrr error 2400 207 0.2% 416 ?0.1% 287 0.0% 575 0.0% 383 0.0% 767 0.0% 4800 103 0.2% 207 0.2% 143 0.0% 287 0.0% 191 0.0% 383 0.0% 9600 51 0.2% 103 0.2% 71 0.0% 143 0.0% 95 0.0% 191 0.0% 14.4k 34 ?0.8% 68 0.6% 47 0.0% 95 0.0% 63 0.0% 127 0.0% 19.2k 25 0.2% 51 0.2% 35 0.0% 71 0.0% 47 0.0% 95 0.0% 28.8k 16 2.1% 34 ?0.8% 23 0.0% 47 0.0% 31 0.0% 63 0.0% 38.4k 12 0.2% 25 0.2% 17 0.0% 35 0.0% 23 0.0% 47 0.0% 57.6k 8 ?3.5% 16 2.1% 11 0.0% 23 0.0% 15 0.0% 31 0.0% 76.8k 6 ?7.0% 12 0.2% 8 0.0% 17 0.0% 11 0.0% 23 0.0% 115.2k 3 8.5% 8 ?3.5% 5 0.0% 11 0.0% 7 0.0% 15 0.0% 230.4k 1 8.5% 3 8.5% 2 0.0% 5 0.0% 3 0.0% 7 0.0% 250k 1 0.0% 3 0.0% 2 ?7.8% 5 ?7.8% 3 ?7.8% 6 5.3% 0.5m 0 0.0% 1 0.0% ? ? 2 ?7.8% 1 ?7.8% 3 ?7.8% 1m ? ? 0 0.0% ? ? ? ? 0 ?7.8% 1 ?7.8% max (1) 0.5mbps 1mbps 691.2kbps 1.3824mbps 921.6kbps 1.8432mbps note: 1. ubrr = 0, error = 0.0% table 19-12. examples of ubrrn setti ngs for commonly used oscill ator frequencies (continued) baud rate (bps) f osc = 16.0000mhz u2xn = 0 u2xn = 1 ubrr error ubrr error 2400 416 ?0.1% 832 0.0% 4800 207 0.2% 416 ?0.1% 9600 103 0.2% 207 0.2% 14.4k 68 0.6% 138 ?0.1% 19.2k 51 0.2% 103 0.2% 28.8k 34 ?0.8% 68 0.6% 38.4k 25 0.2% 51 0.2% 57.6k 16 2.1% 34 ?0.8% 76.8k 12 0.2% 25 0.2% 115.2k 8 ?3.5% 16 2.1% 230.4k 3 8.5% 8 ?3.5% 250k 3 0.0% 7 0.0% 0.5m 1 0.0% 3 0.0% 1m 0 0.0% 1 0.0% max. (1) 1mbps 2mbps note: 1. ubrr = 0, error = 0.0% 169 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 20. usart in spi mode 20.1 features full duplex, three-wire synchronous data transfer master operation supports all four spi modes of operation (mode 0, 1, 2, and 3) lsb first or msb first data transfer (configurable data order) queued operation (double buffered) high resolution baud rate generator high speed operation (fxckmax = fck/2) flexible interrupt generation 20.2 overview the universal synchronous and asynchronous serial receiver a nd transmitter (usart) can be set to a master spi compliant mode of operation. setting both umseln1:0 bits to one enables the usart in mspi m logic. in this mode of operation the spi master control logic takes direct control over the usart resources. these resources include th e transmitter and receiver shift register and buffers, and the baud rate generator. the parity generator and checker, the data and clock recovery logic, and the rx and tx control logic is disabled. the usart rx and tx control logic is replaced by a common spi transf er control logic. however, the pin control logic and interrupt generat ion logic is identical in both modes of operation. the i/o register locations are the same in both modes. however, some of the functionality of the control registers changes when using mspim. 20.3 clock generation the clock generation logic generates the base clock for the transmitter and receiver. for usart mspim mode of operation only internal clock generation (i.e. master operation) is suppor ted. the data direction register for the xckn pin (ddr_xckn) must therefore be set to one (i.e. as output) for the usart in mspim to operate correctly. preferably the ddr_xckn should be set up before the usart in mspim is enabled (i.e. txenn and rxenn bit set to one). the internal clock generation used in mspim mode is identica l to the usart synchronous master mode. the baud rate or ubrrn setting can therefore be calcul ated using the same equations, see table 20-1 : baud baud rate (in bits per second, bps) f osc system oscillator clock frequency ubrrn contents of the ubrrnh and ubrrnl registers, (0-4095 table 20-1. equations for calculat ing baud rate register setting operating mode equation for calculating baud rate (1) equation for calcul ating ubrrn value synchronous master mode note: 1. the baud rate is defined to be the transfer rate in bit per second (bps) baud f osc 2 ubrr n 1 + () ------------------------------------- - = ubrr n f osc 2 baud ------------------- - 1 ? = atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 170 20.4 spi data modes and timing there are four combinations of xckn (s ck) phase and polarity with respect to serial data, which are determined by control bits ucphan and ucpoln. the data transfer timing diagrams are shown in figure 20-1 . data bits are shifted out and latched in on opposite edges of the xckn signal, ensuring sufficient time for data signals to stabilize. the ucpoln and ucphan functionality is summarized in table 20-2 . note that changing the setting of any of these bits will corrupt all ongoing communication for both the receiver and transmitter. figure 20-1. ucphan and ucpoln data transfer timing diagrams 20.5 frame formats a serial frame for the mspim is defined to be one character of 8 data bits. the usart in mspim mode has two valid frame formats: 8-bit data with msb first 8-bit data with lsb first a frame starts with the least or most significant data bit. then the next data bits, up to a total of eight, are succeeding, en ding with the most or least significant bit accordingly. when a comple te frame is transmitted, a new frame can directly follow it, o r the communication line can be set to an idle (high) state. the udordn bit in ucsrnc sets the frame format used by the usart in mspim mode. the receiver and transmitter use the same setting. note that changing t he setting of any of these bits will corr upt all ongoing communication for both the receiver and transmitter. 16-bit data transfer can be achieved by wr iting two data bytes to udrn. a uart transmit complete interrupt will then signal that the 16-bit value has been shifted out. table 20-2. ucpoln and ucphan functionality ucpoln ucphan spi mode leading edge trailing edge 0 0 0 sample (rising) setup (falling) 0 1 1 setup (rising) sample (falling) 1 0 2 sample (falling) setup (rising) 1 1 3 setup (falling) sample (rising) xck ucpol = 0 ucpol = 1 ucpha = 1 ucpha = 0 data setup (txd) data sample (rxd) xck data setup (txd) data sample (rxd) xck data setup (txd) data sample (rxd) xck data setup (txd) data sample (rxd) 171 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 20.5.1 usart mspim initialization the usart in mspim mode has to be initialized before any communication can take place. the initialization process normally consists of setting the baud ra te, setting master mode of operation (by setting ddr_xckn to one), setting frame format and enabling the transmitter and the receiver. only t he transmitter can operate independently. for interrupt driven usart operation, the global interrupt flag should be cleared (and thus interrupts globally disabled) when doing the initialization. note: to ensure immediate initialization of the xckn output th e baud-rate register (ubrrn) must be zero at the time the transmitter is enabled. contrary to the normal mode usart operation the ubrrn must then be written to the desired value after the transmitter is enabled, but bef ore the first transmission is started. setting ubrrn to zero before enabling the transmitter is not necessary if th e initialization is done immediately after a reset since ubrrn is reset to zero. before doing a re-initialization with changed baud rate, data mode, or frame format, be sure that there is no ongoing transmissions during the period the regist ers are changed. the txcn flag can be us ed to check that the transmitter has completed all transfers, and the rxcn flag can be used to che ck that there are no unread data in the receive buffer. note that the txcn flag must be cleared before each transmission (before udrn is written) if it is used for this purpose. the following simple usart initialization code examples sh ow one assembly and one c function that are equal in functionality. the examples assume polling (no interrupts enabled). the baud rate is given as a function parameter. for the assembly code, the baud rate parameter is assu med to be stored in the r17:r16 registers. note: 1. see section 4. ?about code examples? on page 8 . assembly code example (1) usart_init: clr r18 out ubrrnh,r18 out ubrrnl,r18 ; setting the xckn port pin as output, enables master mode. sbi xckn_ddr, xckn ; set mspi mode of operation and spi data mode 0. ldi r18, (1< atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 174 ? bit 6 ? txcn: usart transmit complete this flag bit is set when the entire frame in the transmit shi ft register has been shifted out and there are no new data curren tly present in the transmit buffer (udrn). th e txcn flag bit is automatically cleared when a transmit complete interrupt is executed, or it can be cleared by writin g a one to its bit location. the txcn flag c an generate a transmit complete interrupt (see description of the txcien bit). ? bit 5 ? udren: usart data register empty the udren flag indicates if the transmit buffer (udrn) is ready to receive new data. if udren is one, the buffer is empty, and therefore ready to be written. the udren flag can generat e a data register empty interrupt (see description of the udrie bit). udren is set after a reset to in dicate that the transmitter is ready. ? bit 4:0 ? reserved in mspi mode when in mspi mode, these bits are reserved for future use. fo r compatibility with future devices, these bits must be written to zero when ucsrna is written. 20.8.3 ucsrnb ? usart mspim control and status register n b ? bit 7 ? rxcien: rx complete interrupt enable writing this bit to one enables interrupt on the rxcn flag. a usart receive complete interrupt will be generated only if the rxcien bit is written to one, the global interrupt flag in sreg is written to one and the rxcn bit in ucsrna is set. ? bit 6 ? txcien: tx complete interrupt enable writing this bit to one enables interrupt on the txcn flag. a u sart transmit complete interrupt will be generated only if the txcien bit is written to one, the global interrupt flag in sreg is written to one and the txcn bit in ucsrna is set. ? bit 5 ? udrie: usart data re gister empty interrupt enable writing this bit to one enables interrupt on the udren flag. a data register empty interrupt will be generated only if the udrie bit is written to one, the global interrupt flag in sr eg is written to one and the udren bit in ucsrna is set. ? bit 4 ? rxenn: receiver enable writing this bit to one enables the usart receiver in mspim mode. the receiver will override normal port operation for the rxdn pin when enabled. disabling the receiver will flush the receive buffer. only enabling the receiver in mspi mode (i.e. setting rxenn=1 and txenn=0) has no meaning since it is the transmitter that controls the transfer clock and since only master mode is supported. ? bit 3 ? txenn: transmitter enable writing this bit to one enables the usart transmitter. the tr ansmitter will override normal port operation for the txdn pin when enabled. the disabling of the transmitter (writing txenn to zero) will not become effective until ongoing and pending transmissions are completed, i.e., when the transmit shift regi ster and transmit buffer register do not contain data to be transmitted. when disabled, the transmitter will no longer override the txdn port. ? bit 2:0 ? reserved in mspi mode when in mspi mode, these bits are reserved for future use. fo r compatibility with future devices, these bits must be written to zero when ucsrnb is written. bit 7 6543210 rxcien txcien udrie rxenn txenn ? ? ? ucsrnb read/write r/w r/w r/w r/w r/w r r r initial value 0 0 0 0 0 1 1 0 175 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 20.8.4 ucsrnc ? usart mspim control and status register n c ? bit 7:6 ? umseln1:0: usart mode select these bits select the mode of operation of the usart as shown in table 20-4 . see section 19.11.4 ?ucsrnc ? usart control and status register n c? on page 165 for full description of the normal usart operation. the mspim is enabled when both umseln bits are set to one. the udordn, ucphan, a nd ucpoln can be set in the same write operation where the mspim is enabled. ? bit 5:3 ? reserved in mspi mode when in mspi mode, these bits are reserved for future use. fo r compatibility with future devices, these bits must be written to zero when ucsrnc is written. ? bit 2 ? udordn: data order when set to one the lsb of the data word is transmitted first. when set to zero the msb of the data word is transmitted first. refer to the frame formats section page 4 for details. ? bit 1 ? ucphan: clock phase the ucphan bit setting determine if data is sampled on the leas ing edge (first) or tailing (last) edge of xckn. refer to the spi data modes and timing section page 4 for details. ? bit 0 ? ucpoln: clock polarity the ucpoln bit sets the polarity of the xckn clock. the combination of the ucpoln and ucphan bit settings determine the timing of the data transfer. refer to the spi data modes and timing section page 4 for details. 20.8.5 ubrrnl and ubrrnh ?usart mspim baud ra te registers the function and bit description of the baud rate registers in mspi mode is identical to normal usart operation. see section 19.11.5 ?ubrrnl and ubrrnh ? usart baud rate registers? on page 166 . bit 7 6 543 2 1 0 umseln1 umseln0 ? ? ? udordn ucphan ucpoln ucsrnc read/write r/w r/w r r r r/w r/w r/w initial value 0 0 0 0 0 1 1 0 table 20-4. umseln bits settings umseln1 umseln0 mode 0 0 asynchronous usart 0 1 synchronous usart 1 0 (reserved) 1 1 master spi (mspim) atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 176 21. two-wire serial interface 21.1 features simple yet powerful and flexible communication interface, only two bus lines needed both master and slave operation supported device can operate as transmitter or receiver 7-bit address space allows up to 128 different slave addresses multi-master arbitration support up to 400khz data transfer speed slew-rate limited output drivers noise suppression circuitry rejects spikes on bus lines fully programmable slave address with general call support address recognition causes wake-up when avr ? is in sleep mode 21.2 two-wire serial interface bus definition the two-wire serial interface (twi) is id eally suited for typical microcontroller applications. the twi pr otocol allows the systems designer to interconnect up to 128 different devices using only two bi-directional bus lines, one for clock (scl) and one for data (sda). the only external hardware needed to implem ent the bus is a single pull-up re sistor for each of the twi bus lines. all devices connected to the bus have individual addresses, and mechanisms for resolving bus contention are inherent in the twi protocol. figure 21-1. twi bus interconnection 21.2.1 twi terminology the following definitions are frequently encountered in this section. the power reduction twi bit, prtwi bit in section 10.12.3 ?prr0 ? power reduction register 0? on page 39 must be written to zero to enable the 2-wire serial interface. device 1 sda scl v cc device 2 device 3 device n ........ r1 r2 table 21-1. twi terminology term description master the device that initiates and terminates a transmi ssion. the master also generates the scl clock slave the device addressed by a master transmitter the device placing data on the bus receiver the device reading data from the bus 177 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 21.2.2 electrical interconnection as depicted in figure 21-1 on page 176 , both bus lines are connec ted to the positive supply voltage through pull-up resistors. the bus drivers of all twi-compliant devices are open-drain or open-collector. this implements a wired-and function which is essential to t he operation of the interface. a low level on a twi bus line is generated when one or more twi devices output a zero. a high level is out put when all twi devices trim-state their outputs, allowing the pull-up resistors to pull the line high. note that all avr ? devices connected to the twi bus must be powered in order to allow any bus operation. the number of devices that can be connecte d to the bus is only limited by the bus capacitance limit of 400pf and the 7-bit slave address space. a detailed spec ification of the electrical charac teristics of the twi is given in section 28.7 ?spi timing characteristics? on page 292 . two different sets of specifications are pres ented there, one relevant for bus speeds below 100khz, and one valid for bus speeds up to 400khz. 21.3 data transfer and frame format 21.3.1 transferring bits each data bit transferred on the twi bus is accompanied by a pulse on the clock line. the level of the data line must be stable when the clock line is high. the only exception to this rule is for generat ing start and stop conditions. figure 21-2. data validity 21.3.2 start and stop conditions the master initiates and terminates a data transmission. the transmission is in itiated when the master issues a start condition on the bus, and it is termina ted when the master issues a stop condition. between a start and a stop condition, the bus is considered busy, and no other master should try to seize control of the bus. a special case occurs when a new start condition is issued between a start and stop condition. this is referred to as a repeated start condition, and is used when the master wi shes to initiate a new transfer without relinquishing control of the bus. after a repeated start, the bus is considered bu sy until the next stop. this is identic al to the start behavior, and therefore start is used to describe both start and repeated start for the remainder of this datasheet, unl ess otherwise noted. as depicted below, start and stop conditions are signa lled by changing the level of the sda line when the scl line is high. figure 21-3. start, repeated start and stop conditions sda scl data stable data change data stable sda scl start start repeated start stop stop atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 178 21.3.3 address packet format all address packets transmitted on the twi bus are 9 bits long , consisting of 7 address bits, one read/write control bit and an acknowledge bit. if the read/write bit is set, a re ad operation is to be performe d, otherwise a write operation should be performed. when a slave recognizes that it is being addressed, it should acknowledge by pulling sda low in the ninth scl (ack) cycle. if the addressed slave is busy, or for some other reason can not service the master?s request, the sda line should be left high in the ack clock cycle. the master can then tran smit a stop condition, or a repeated start condition to initiate a new transmission. an address packet consisting of a slave address and a read or a write bit is called sla+r or sla+w, respectively. the msb of the address byte is transmitted first. slave addres ses can freely be allocated by the designer, but the address 0000 000 is reserved for a general call. when a general call is issued, all slaves should respond by pulling the sda line low in the ack cycle. a general call is used when a master wishes to transmit the same message to several slaves in th e system. when the gener al call address followed by a write bit is transmitted on t he bus, all slaves set up to acknowledge the general call will pull the sda line low in the ack cycle. the following data packets will then be received by all the slaves that acknowledged the general call. note that transmitting the general call address followed by a read bit is meaningless, as this would cause contention if several slaves started transmitting different data. all addresses of the format 1111 xxx shou ld be reserved for future purposes. figure 21-4. address packet format 21.3.4 data packet format all data packets transmitted on the twi bus are nine bits long , consisting of one data byte and an acknowledge bit. during a data transfer, the master generat es the clock and the start and stop conditions, while the receiver is responsible for acknowledging the reception. an acknowledge (ack) is signal led by the receiver pulling the sda line low during the ninth scl cycle. if the receiver leaves the sda line high, a nack is signalled. when the receiver has received the last byte, or for some reason cannot receive any more bytes, it should info rm the transmitter by sending a nack after the final byte. the msb of the data byte is transmitted first. sda scl start addr msb addr lsb r/w ack 12 789 179 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 figure 21-5. data packet format 21.3.5 combining address and data packets into a transmission a transmission basically consists of a start condition, a sla+ r/w, one or more data packets and a stop condition. an empty message, consisting of a start follo wed by a stop condition, is illegal. note that the wired-anding of the scl line can be used to implement handshaking betw een the master and the slave. the sl ave can extend the scl low period by pulling the scl line low. this is useful if the clock speed set up by the master is too fast fo r the slave, or the slave needs extra time for processing between the data transmissions. t he slave extending the scl low pe riod will not affect the scl high period, which is determined by the master. as a consequ ence, the slave can reduce th e twi data transfer speed by prolonging the scl duty cycle. figure 21-6 shows a typical data transmission. note that severa l data bytes can be transmitted between the sla+r/w and the stop condition, depending on the software prot ocol implemented by the application software. figure 21-6. typical data transmission 21.4 multi-master bus systems, arbitration and synchronization the twi protocol al lows bus systems with several mast ers. special concerns have been taken in order to ensure that transmissions will proceed as normal, even if two or more mast ers initiate a transmission at the same time. two problems arise in multi-master systems: an algorithm must be implemented allowing only one of t he masters to complete the transmission. all other masters should cease transmission when they disco ver that they have lost the selecti on process. this selection process is called arbitration. when a contending master discovers that it has lost the arbi tration process, it should immediately switch to slave mode to check whether it is being addre ssed by the winning master. the fact that multiple masters have started transmission at the same time should not be det ectable to the slaves, i.e. the data being transferred on the bus must not be corrupted. aggregate sda sda from transmitter sda from receiver scl from master data msb data lsb ack 12 7 data byte stop, repeated start or next data byte sla + r/w 89 sda scl stop start sla + r/w data byte addr msb addr lsb data msb data lsb ack r/w ack 12 789 12 789 atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 180 different masters may use different sc l frequencies. a scheme must be devised to synchronize the serial clocks from all masters, in order to let the transmission proceed in a lockstep fashi on. this will facilit ate the arbitration process. the wired-anding of the bus lines is used to solve both these problems. the seri al clocks from all masters will be wired- anded, yielding a combined clock with a high period equal to the one from the master with the shortest high period. the low period of the combined clock is equal to the low period of the master with the longest low period. note that all masters listen to the scl line, effectively starting to count their scl high a nd low time-out periods when the combined scl line goes high or low, respectively. figure 21-7. scl synchronization between multiple masters arbitration is carried out by all masters continuously monitori ng the sda line after outputting data. if the value read from th e sda line does not match the value the master had output, it has lost the arbitration. note that a master can only lose arbitration when it outputs a high sda va lue while another master outputs a low value. the losing master should immediately go to slave mode, checking if it is being addressed by the winning master. the sda line should be left high, but losing masters are allowed to generate a clock signal until t he end of the current data or address packet. arbitration will continue until only one master remains, and this may take many bits. if several masters are tr ying to address the same slave, arbitration will contin ue into the data packet. figure 21-8. arbitration between two masters scl from master a scl from master b scl bus line masters start counting low period masters start counting high period ta low ta high tb low tb high sda from master a sda from master b synchronized scl line sda line start master a loses arbitration, sda a sda 181 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 note that arbitration is not allowed between: a repeated start condition and a data bit. a stop condition and a data bit. a repeated start and a stop condition. it is the user software?s responsibility to ensure that these il legal arbitration conditions never occur. this implies that in multi-master systems, all data transfers must use the same composition of sla+r/ w and data packets. in other words: all transmissions must contain the same number of data packets , otherwise the result of t he arbitration is undefined. 21.5 overview of the twi module the twi module is comprised of several submodules, as shown in figure 21-9 . all registers drawn in a thick line are accessible through the avr ? data bus. figure 21-9. overview of the twi module start/ stop control spike filter slew-rate control address/ data shift register (twdr) arbitration detection spike suppression bit rate register (twbr) prescaler ack bus interface unit scl spike filter slew-rate control sda bit rate generator address register (twar) address comparator address match unit status register (twsr) control register (twcr) state machine and status control control unit twi unit atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 182 21.5.1 scl and sda pins these pins interface the avr ? twi with the re st of the mcu system. the ou tput drivers contain a slew -rate limiter in order to conform to the twi specification. the inpu t stages contain a spike suppression unit removing spikes shorter than 50ns. note that the internal pull-ups in the avr p ads can be enabled by setting the port bits corresponding to the scl and sda pins, as explained in the i/o port section. the internal pull-ups can in some systems eliminate the need for external ones. 21.5.2 bit rate generator unit this unit controls the period of scl when operating in a master mode. the scl period is controlled by settings in the twi bit rate register (twbr) and the prescaler bits in the twi status register (twsr). slave operation does not depend on bit rate or prescaler settings, but the cpu clock frequency in the slave must be at least 16 times higher than the scl frequency. note that slaves may prolong the scl lo w period, thereby reducing the average tw i bus clock period. the scl frequency is generated according to the following equation: twbr = value of the twi bit rate register. twps = value of the prescaler bits in the twi status register. note: pull-up resistor values should be selected according to the scl frequency and the capacitive bus line load. see 2-wire serial bus requirements in table 28-9 on page 293 for value of pull-up resistor. 21.5.3 bus interface unit this unit contains the data and address shift register (twdr) , a start/stop controller and arbitration detection hardware. the twdr contains the address or data bytes to be transmitted, or the address or data bytes received. in addition to the 8-bit twdr, the bus interface unit also contains a register containing the (n)ack bit to be transmitted or received. this (n)ack register is not directly accessible by the application so ftware. however, when receiving, it can be set or cleared by manipulating the twi control register (twcr). when in tr ansmitter mode, the value of the received (n)ack bit can be determined by the value in the twsr. the start/stop controller is responsible for generatio n and detection of start, repeated start, and stop conditions. the start/stop controller is able to detect start and stop conditions even when the avr mcu is in one of the sleep modes, enabling the mcu to wake up if addressed by a master. if the twi has initiated a transmission as master, the arbitrat ion detection hardware continuous ly monitors the transmission trying to determine if arbitration is in process. if the twi has lost an arbitration, the control unit is informed. correct act ion can then be taken and appropriate status codes generated. 21.5.4 address match unit the address match unit checks if received address bytes match the seven-bit addre ss in the twi address register (twar). if the twi general call recognition enable (twgce) bit in the tw ar is written to one, all incoming address bits will also be compared against the general call address. upon an address matc h, the control unit is informed, allowing correct action to be taken. the twi may or may not acknowledge its address, dep ending on settings in the twcr. the address match unit is able to compare addresses even when the avr mcu is in sleep mode, enabling the mcu to wake up if addressed by a master. 21.5.5 control unit the control unit monitors the twi bus and generates responses corresponding to settings in the twi control register (twcr). when an event requiring the attention of the applicat ion occurs on the twi bus, the twi interrupt flag (twint) is asserted. in the next clock cycle, the twi status register (twsr) is updated with a status code identifying the event. the twsr only contains relevant status information when the tw i interrupt flag is asserted. at all other times, the twsr contains a special status code indicating that no relevant status inform ation is available. as long as the twint flag is set, t he scl line is held low. this allows the application software to co mplete its tasks before allo wing the twi transmission to continue. scl frequency cpu clock frequency 16 2(twbr) 4 twps ? + --------------------------------------------------------- = 183 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 the twint flag is set in the following situations: after the twi has transmitted a start/repeated start condition. after the twi has transmitted sla+r/w. after the twi has transmitted an address byte. after the twi has lost arbitration. after the twi has been addressed by own slave address or general call. after the twi has received a data byte. after a stop or repeated start has been received while still addressed as a slave. when a bus error has occurred due to an illegal start or stop condition. 21.6 using the twi the avr ? twi is byte-oriented and interrupt based. interrupts are i ssued after all bus events, like reception of a byte or transmission of a start condition. because the twi is interr upt-based, the applicat ion software is free to carry on other operations during a twi byte transfer. note that the twi inte rrupt enable (twie) bit in twcr together with the global interrupt enable bit in sreg allow the application to decide wh ether or not assertion of the twint flag should generate an interrupt request. if the twie bit is cleared, the application mu st poll the twint flag in order to detect actions on the twi bus. when the twint flag is asserted, the twi has finished an operati on and awaits application response. in this case, the twi status register (twsr) contains a value indicating the curr ent state of the twi bus. the application software can then decide how the twi should behave in the next twi bus cycle by m anipulating th e twcr and twdr registers. figure 21-10 is a simple example of how the application can interface to the twi hardware. in this example, a master wishes to transmit a single data byte to a slave. this description is quite abstract, a more detailed explanation follows later in thi s section. a simple code example implementi ng the desired behavior is also presented. figure 21-10. interfacing the application to the twi in a typical transmission 1. the first step in a twi transmission is to transmit a star t condition. this is done by writing a specific value into twcr, instructing the twi hardware to transmit a start condition. which value to write is described later on. however, it is important that the twin t bit is set in the value written. writing a one to twint clears the flag. the twi will not start any operation as l ong as the twint bit in twcr is set. immediately after the application has cleared twint, the twi will initiate transmission of the start condition. 2. when the start condition has been transmitted, the twin t flag in twcr is set, and twsr is updated with a status code indicating that the star t condition has successfully been sent. start twi hardware action application action twi bus indicates twint set sla + w a a stop data 1. application writes to twcr to initiate transmission of start 2. twint set. status code indicates start condition sent 4. twint set. status code indicates sla + w sent, ack received 6. twint set. status code indicates data sent, ack received 3. check twsr to see if start was sent. application loads sla + w into twdr, and loads appropriate control signals into twcr, makin sure that twint is written to one, and twsta is written to zero. 5. check twsr to see if sla + w was sent and ack received. application loads data intotwdr, and loads appropriate control signals into twcr, makin sure that twint is written to one 7. check twsr to see if data was sent and ack received. application loads appropriate control signals to send stop into twcr, makin sure that twint is written to one atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 184 3. the application software should now examine the value of twsr, to make sure that the start condition was successfully transmitted. if twsr indicates otherwise, the application software might take some special action, like calling an error routine. assuming that the status co de is as expected, the applic ation must load sla+w into twdr. remember that twdr is used both for address a nd data. after twdr has been loaded with the desired sla+w, a specific value must be written to twcr, instru cting the twi hardware to transmit the sla+w present in twdr. which value to write is described later on. however, it is important that the twint bit is set in the value written. writing a one to twint clears the flag. the twi will not start any o peration as long as the twint bit in twcr is set. immediately after the application has cleared twint, the tw i will initiate transmission of the address packet. 4. when the address packet has been transmitted, the tw int flag in twcr is set, and twsr is updated with a status code indicating that the address packet has su ccessfully been sent. the status code will also reflect whether a slave acknowledged the packet or not. 5. the application software should now examine the value of twsr, to make sure that the address packet was successfully transmitted, an d that the value of the ack bit was as expected. if twsr indicates otherwise, the application software might take some special action, like ca lling an error routine. assu ming that the status code is as expected, the application mu st load a data packet into twdr. subsequen tly, a specific valu e must be written to twcr, instructing the twi hardware to transmit the data packet present in twdr. which value to write is described later on. however, it is important that the twint bit is set in the value written. writing a one to twint clears the flag. the twi will not start any operation as long as the twint bit in twcr is set. immediately after the application has cleared twint, the twi will initiate transmission of the data packet. 6. when the data packet has been transmitted, the twint flag in twcr is set, and twsr is updated with a status code indicating that the data packet has successfully been sent. the status code will also reflect whether a slave acknowledged the packet or not. 7. the application software should now examine the value of twsr, to make sure that the data packet was successfully transmitted, an d that the value of the ack bit was as expected. if twsr indicates otherwise, the application software might take some special action, like ca lling an error routine. assu ming that the status code is as expected, the application must write a specific value to twcr, in structing the twi hardware to transmit a stop condition. which value to write is described later on. ho wever, it is important that the twint bit is set in the value written. writing a one to twint clears the flag. the twi will not start any operation as long as the twint bit in twcr is set. immediately after t he application has cleared twint, the twi will initiate transmission of the stop condition. note that twint is not set after a stop condition has been sent. even though this example is simple, it show s the principles involved in all twi transmissions. these can be summarized as follows: when the twi has finished an operation and expects application response, the twint flag is set. the scl line is pulled low until twint is cleared. when the twint flag is set, the user mu st update all twi r egisters with the va lue relevant for t he next twi bus cycle. as an example, twdr must be lo aded with the value to be tran smitted in the next bus cycle. after all twi register updates and other pending applicat ion software tasks have been completed, twcr is written. when writing twcr, the twint bit should be set. writ ing a one to twint clears the flag. the twi will then commence executing whatever operatio n was specified by the twcr setting. 185 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 in the following an assembly and c implemen tation of the example is given. note th at the code below assumes that several definitions have been made, for ex ample by using include-files. table 21-2. assembly code example assembly code example c example comments 1 ldi r16, (1< 187 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 a start condition is sent by wr iting the following value to twcr: twen must be set to enable the 2-wire serial interface, tw sta must be written to one to transmit a start condition and twint must be written to one to clear the twint flag. the twi will then test the 2-wire serial bus and generate a start condition as soon as the bus becomes free. after a start co ndition has been transmitted, the twint flag is set by hardware, and the status code in twsr will be 0x08 (see table 21-3 ). in order to enter mt mode, sla+w must be transmitted. this is done by writing sla+w to twdr. thereaft er the twint bit should be cleared (by writing it to one) to continue the transfer. this is accomplis hed by writing the following value to twcr: when sla+w have been transmitted and an ack nowledgement bit has been received, tw int is set again and a number of status codes in twsr are possible. possible status codes in master mode are 0x18, 0x20, or 0x38. the appropriate action to be taken for each of these status codes is detailed in table 21-3 . when sla+w has been successfully transmitte d, a data packet should be transmitted. th is is done by writing the data byte to twdr. twdr must only be written when twint is high. if not, the access will be discard ed, and the write collision bit (twwc) will be set in the twcr register. after updating twdr, th e twint bit should be cleared (by writing it to one) to continue the transfer. this is accomplis hed by writing the following value to twcr: this scheme is repeated until the last byte has been sent and the transfer is ended by gener ating a stop condition or a repeated start condition. a stop condition is ge nerated by writing the following value to twcr: a repeated start condition is generated by writing th e following value to twcr: after a repeated start condition (state 0x10) the 2-wire serial interface can access the same slave again, or a new slave without transmitting a stop condition. re peated start enables the master to swit ch between slaves, master transmitter mode and master receiver mode wit hout losing control of the bus. twcr twint twea twsta twsto twwc twen ? twie value 1 x10 x1 0 x twcr twint twea twsta twsto twwc twen ? twie value 1 x00 x1 0 x twcr twint twea twsta twsto twwc twen ? twie value 1 x00 x1 0 x twcr twint twea twsta twsto twwc twen ? twie value 1 x01 x1 0 x twcr twint twea twsta twsto twwc twen ? twie value 1 x10 x1 0 x atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 188 table 21-3. status codes for master transmitter mode status code (twsr) prescaler bits are 0 status of the 2-wire serial bus and 2-wire serial interface hardware application software response next action taken by twi hardware to/from twdr to twcr sta sto twint twea 0x08 a start condition has been transmitted load sla+w 0 0 1 x sla+w will be transmitted; ack or not ack will be received 0x10 a repeated start condition has been transmitted load sla+w or load sla+r 0 0 0 0 1 1 x x sla+w will be transmitted; ack or not ack will be received sla+r will be transmitted; logic will switch to master receiver mode 0x18 sla+w has been transmitted; ack has been received load data byte or no twdr action or no twdr action or no twdr action 0 1 0 1 0 0 1 1 1 1 1 1 x x x x data byte will be transmitted and ack or not ack will be received repeated start will be transmitted stop condition will be transmitted and twsto flag will be reset stop condition followed by a start condition will be transmitted and twsto flag will be reset 0x20 sla+w has been transmitted; not ack has been received load data byte or no twdr action or no twdr action or no twdr action 0 1 0 1 0 0 1 1 1 1 1 1 x x x x data byte will be transmitted and ack or not ack will be received repeated start will be transmitted stop condition will be transmitted and twsto flag will be reset stop condition followed by a start condition will be transmitted and twsto flag will be reset 0x28 data byte has been transmitted; ack has been received load data byte or no twdr action or no twdr action or no twdr action 0 1 0 1 0 0 1 1 1 1 1 1 x x x x data byte will be transmitted and ack or not ack will be received repeated start will be transmitted stop condition will be transmitted and twsto flag will be reset stop condition followed by a start condition will be transmitted and twsto flag will be reset 0x30 data byte has been transmitted; not ack has been received load data byte or no twdr action or no twdr action or no twdr action 0 1 0 1 0 0 1 1 1 1 1 1 x x x x data byte will be transmitted and ack or not ack will be received repeated start will be transmitted stop condition will be transmitted and twsto flag will be reset stop condition followed by a start condition will be transmitted and twsto flag will be reset 0x38 arbitration lost in sla+w or data bytes no twdr action or no twdr action 0 1 0 0 1 1 x x 2-wire serial bus will be released and not addressed slave mode entered a start condition will be transmitted when the bus becomes free 189 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 figure 21-12. formats and states in the master transmitter mode s successfull transmission to a slave receiver next transfer started with a repeated start condition not acknowledge received after the slave address not acknowledge received after a data byte arbitration lost and addressed as slave from master to slave any number of data bytes and their associated acknowledge bits this number (contained in twsr) corresponds to a defined state of the two-wire serial bus. the prescaler bits are zero or masked to zero from slave to master arbitration lost in slave address or data byte sla w r s sla w aap ap r mr mt data a data $08 $18 $20 $38 $28 ap $30 $38 $10 a or a other master continues $68 $78 n a other master continues to corresponding states in slave mode a or a other master continues $b0 atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 190 21.7.2 master receiver mode in the master receiver mode, a number of data by tes are received from a slave transmitter (slave see figure 21-13 ). in order to enter a master mode, a start condit ion must be transmitted. the format of the following address packet determines whether master transmitter or master receiver mode is to be entered. if sla+w is transmitted, mt mode is entered, if sla+r is transmitted, mr mode is entered. all the status codes mentioned in this section assume that the prescaler bits are zero or are masked to zero. figure 21-13. data transfer in master receiver mode a start condition is sent by wr iting the following value to twcr: twen must be written to one to enable the 2-wire serial inte rface, twsta must be written to one to transmit a start condition and twint must be set to clear the twint flag. th e twi will then test the 2-wire serial bus and generate a start condition as soon as the bus become s free. after a start condition has been transmitted, the twint flag is set by hardware, and the status co de in twsr will be 0x08 (see table 21-3 on page 188 ). in order to enter mr mode, sla+r must be transmitted. this is done by writing sl a+r to twdr. thereafter the twint bit shou ld be cleared (by writing it to one) to continue the transfer. this is accomplis hed by writing the following value to twcr: when sla+r have been transmitted and an acknowledgement bit has been received, twint is set again and a number of status codes in twsr are possible. possible status codes in master mode are 0x38, 0x40, or 0x48. the appropriate action to be taken for each of these status codes is detailed in table 21-4 on page 191 . received data can be read from the twdr register when the twint flag is set high by hardware. this scheme is repeated until the last byte has been received. after the last byte has been received, the mr should inform the st by sending a nack after the last received data byte. the transfer is ended by generating a stop c ondition or a repeated start condition. a stop condition is generated by writing the following value to twcr: a repeated start condition is generated by writing th e following value to twcr: twcr twint twea twsta twsto twwc twen ? twie value 1 x10 x1 0 x twcr twint twea twsta twsto twwc twen ? twie value 1 x00 x1 0 x twcr twint twea twsta twsto twwc twen ? twie value 1 x01 x1 0 x twcr twint twea twsta twsto twwc twen ? twie value 1 x10 x1 0 x device 1 master receiver sda scl v cc device 3 device n ........ r1 r2 device 2 slave transmitter 191 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 after a repeated start condition (state 0x10) the 2-wire serial interface can access the same slave again, or a new slave without transmitting a stop condition. re peated start enables the master to swit ch between slaves, master transmitter mode and master receiver mode wit hout losing control over the bus. table 21-4. status codes for master receiver mode status code (twsr) prescaler bits are 0 status of the 2-wire serial bus and 2-wire serial interface hardware application software response next action taken by twi hardware to/from twdr to twcr sta sto twint twea 0x08 a start condition has been transmitted load sla+r 0 0 1 x sla+r will be transmitted ack or not ack will be received 0x10 a repeated start condition has been transmitted load sla+r or load sla+w 0 0 0 0 1 1 x x sla+r will be transmitted ack or not ack will be received sla+w will be transmitted logic will switch to master transmitter mode 0x38 arbitration lost in sla+r or not ack bit no twdr action or no twdr action 0 1 0 0 1 1 x x 2-wire serial bus will be released and not addressed slave mode will be entered a start condition will be transmitted when the bus becomes free 0x40 sla+r has been transmitted; ack has been received no twdr action or no twdr action 0 0 0 0 1 1 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 0x48 sla+r has been transmitted; not ack has been received no twdr action or no twdr action or no twdr action 1 0 1 0 1 1 1 1 1 x x x repeated start will be transmitted stop condition will be transmitted and twsto flag will be reset stop condition followed by a start condition will be trans mitted and twsto flag will be reset 0x50 data byte has been received; ack has been returned read data byte or read data byte 0 0 0 0 1 1 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 0x58 data byte has been received; not ack has been returned read data byte or read data byte or read data byte 1 0 1 0 1 1 1 1 1 x x x repeated start will be transmitted stop condition will be transmitted and twsto flag will be reset stop condition followed by a start condition will be trans mitted and twsto flag will be reset atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 192 figure 21-14. formats and states in the master receiver mode 21.7.3 slave receiver mode in the slave receiver mode, a number of data byte s are received from a master transmitter (see figure 21-15 ). all the status codes mentioned in this section a ssume that the prescaler bits are zero or are masked to zero. figure 21-15. data transfer in slave receiver mode s successfull reception from a slave receiver next transfer started with a repeated start condition not acknowledge received after the slave address arbitration lost and addressed as slave arbitration lost in slave address or data byte from master to slave any number of data bytes and their associated acknowledge bits this number (contained in twsr) corresponds to a defined state of the two-wire serial bus. the prescaler bits are zero or masked to zero from slave to master sla r r s sla r a data ap ap w mt mr data a data $08 $40 $48 $38 $50 $58 $38 $10 a a or a other master continues $68 $78 n a other master continues to corresponding states in slave mode a or a other master continues $b0 device 1 slave receiver sda v cc scl device 3 device n ........ r1 r2 device 2 master transmitter 193 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 to initiate the slave receiver mode, twar and twcr must be initialized as follows: the upper 7 bits are the address to which the 2-wire serial interface will respond when addressed by a master. if the lsb is set, the twi will respond to the general call addre ss (0x00), otherwise it will i gnore the general call address. twen must be written to one to enable the twi. the twea bit must be written to one to enable the acknowledgement of the device?s own slave address or the general call address. twsta and twsto must be written to zero. when twar and twcr have been initialized, the twi waits unti l it is addressed by its own slave address (or the general call address if enabled) followed by the data direction bit. if the direction bit is ?0? (write), the twi will operate in sr mo de, otherwise st mode is entered. after its own slave address and the write bit have b een received, the twint flag is set and a valid status code can be read from twsr . the status code is used to determine the appropriate software action. the appropriate action to be taken for ea ch status code is detailed in table 21-5 on page 193 . the slave receiver mode may also be entered if arbitration is lost while the twi is in the master mode (see states 0x68 and 0x78). if the twea bit is reset during a transfer, the twi will return a ?not acknowledge? (?1?) to sda after the next received data byte. this can be used to indicate that the slave is not able to receive any more bytes. while twea is zero, the twi does not acknowledge its own slave address. however, the 2-wire serial bus is still monitored and address recognition may resume at any time by setting twea. this implies that the twea bit may be used to temporarily isolate t he twi from the 2-wire serial bus. in all sleep modes other th an idle mode, the clock system to th e twi is turned off. if the twea bit is set, the interface can s till acknowledge its own slave address or the general call address by using the 2-wire serial bus clock as a clock source. the part will then wake up from sleep and the twi will hold the sc l clock low during the wake up and until the twint flag is cleared (by writing it to one). further data reception will be carried out as normal, with the avr ? clocks running as normal. observe that if the avr is set up with a long start-up time, the scl line may be held low for a long time, blocking other data transmissions. note that the 2-wire serial interface data regi ster ? twdr does not reflect the last byte present on the bus when waking up from these sleep modes. twar twa6 twa5 twa4 twa3 twa2 twa1 twa0 twgce value device?s own slave address twcr twint twea twsta twsto twwc twen ? twie value 0 100 01 0 x table 21-5. status codes for slave receiver mode status code (twsr) prescaler bits are 0 status of the 2-wire serial bus and 2-wire serial interface hardware application software response next action taken by twi hardware to/from twdr to twcr sta sto twint twea 0x60 own sla+w has been received; ack has been returned no twdr action or no twdr action x x 0 0 1 1 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 0x68 arbitration lost in sla+r/w as master; own sla+w has been received; ack has been returned no twdr action or no twdr action x x 0 0 1 1 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 0x70 general call address has been received; ack has been returned no twdr action or no twdr action x x 0 0 1 1 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 0x78 arbitration lost in sla+r/w as master; general call address has been received; ack has been returned no twdr action or no twdr action x x 0 0 1 1 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 0x80 previously addressed with own sla+w; data has been received; ack has been returned read data byte or read data byte x x 0 0 1 1 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 194 0x88 previously addressed with own sla+w; data has been received; not ack has been returned read data byte or read data byte or read data byte or read data byte 0 0 1 1 0 0 0 0 1 1 1 1 0 1 0 1 switched to the not addressed slave mode; no recognition of own sla or gca switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1? switched to the not addressed slave mode; no recognition of own sla or gca; a start condition will be transmitted when the bus becomes free switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1?; a start condition will be transmitted when the bus becomes free 0x90 previously addressed with general call; data has been received; ack has been returned read data byte or read data byte x x 0 0 1 1 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 0x98 previously addressed with general call; data has been received; not ack has been returned read data byte or read data byte or read data byte or read data byte 0 0 1 1 0 0 0 0 1 1 1 1 0 1 0 1 switched to the not addressed slave mode; no recognition of own sla or gca switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1? switched to the not addressed slave mode; no recognition of own sla or gca; a start condition will be transmitted when the bus becomes free switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1?; a start condition will be transmitted when the bus becomes free 0xa0 a stop condition or repeated start condition has been received while still addressed as slave no action 0 0 1 1 0 0 0 0 1 1 1 1 0 1 0 1 switched to the not addressed slave mode; no recognition of own sla or gca switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1? switched to the not addressed slave mode; no recognition of own sla or gca; a start condition will be transmitted when the bus becomes free switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1?; a start condition will be transmitted when the bus becomes free table 21-5. status codes for sla ve receiver mode (continued) status code (twsr) prescaler bits are 0 status of the 2-wire serial bus and 2-wire serial interface hardware application software response next action taken by twi hardware to/from twdr to twcr sta sto twint twea 195 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 figure 21-16. formats and states in the slave receiver mode s reception of the own slave address and one or more data bytes. all are acknowledged last data byte received is not acknowledged last data byte received is not acknowledged arbitration lost as master and addressed as slave arbitration lost as master and as slave by general call from master to slave any number of data bytes and their associated acknowledge bits this number (contained in twsr) corresponds to a defined state of the two-wire serial bus. the prescaler bits are zero or masked to zero from slave to master sla w a data ap or s a data a data $60 $68 $80 $80 $a0 $88 a p or s a n $90 $90 $a0 $98 p or s a reception of the general call address and one or more data bytes a $70 general call data ap or s a data $78 a atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 196 21.7.4 slave transmitter mode in the slave transmitter mode, a number of data by tes are transmitted to a master receiver (see figure 21-17 ). all the status codes mentioned in this section a ssume that the prescaler bits are zero or are masked to zero. figure 21-17. data transfer in slave transmitter mode to initiate the slave transmitter mode, tw ar and twcr must be initialized as follows: the upper seven bits are the address to which the 2-wire seri al interface will respond when addressed by a master. if the lsb is set, the twi will respond to the general call address (0x00), otherwise it will ignore the general call address. twen must be written to one to enable the twi. the twea bit must be written to one to enable the acknowledgement of the device?s own slave address or the general call address. twsta and twsto must be written to zero. when twar and twcr have been initialized, the twi waits unti l it is addressed by its own slave address (or the general call address if enabled) followed by the data direction bit. if the direction bit is ?1? (read), the twi will operate in st mod e, otherwise sr mode is entered. after its own slave address and the write bit have been received, the twint flag is set and a valid status code can be read from twsr . the status code is used to determine the appropriate software action. the appropriate action to be taken for each status code is detailed in table 21-6 on page 197 . the slave transmitter mode may also be entered if arbitration is lost while the twi is in the master mode (see state 0xb0). if the twea bit is written to zero during a transfer, the twi will transmit the last byte of the transfer. state 0xc0 or state 0xc8 will be entered, depending on whether the ma ster receiver transmits a nack or ack after the final byte. the twi is switched to the not addressed slave mode, and will ignore the master if it continues the transfer. thus the master receiver receives all ?1? as serial data. state 0xc8 is entered if the master demands additi onal data bytes (by transmitting ack), even though the slave has transmitted the last byte (twea zero and expecting nack from the master). while twea is zero, the twi does not respond to its own slave address. however, the 2-wire se rial bus is still monitored and address recognition may resume at any time by sett ing twea. this implies that the twea bit may be used to temporarily isolate the twi from the 2-wire serial bus. in all sleep modes other than idle mode, the clock system to the twi is turned off. if the twea bit is set, the interface can still acknowledge its own slave address or the general call addr ess by using the 2-wire serial bus clock as a clock source. the part will then wake up from sleep and the twi will hold the scl clock will low during the wake up and until the twint flag is cleared (by writing it to one). further data trans mission will be carried out as normal, with the avr ? clocks running as normal. observe that if the avr is set up with a long start-up time, the scl line may be held low for a long time, blocking other data transmissions. note that the 2-wire serial interface data register ? twdr does not reflect the last byte present on the bus when waking up from these sleep modes. twar twa6 twa5 twa4 twa3 twa2 twa1 twa0 twgce value device?s own slave address twcr twint twea twsta twsto twwc twen ? twie value 0 100 01 0 x device 1 slave transmitter sda v cc scl device 3 device n ........ r1 r2 device 2 master receiver 197 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 table 21-6. status codes for slave transmitter mode status code (twsr) prescaler bits are 0 status of the 2-wire serial bus and 2-wire serial interface hardware application software response next action taken by twi hardware to/from twdr to twcr sta sto twint twea 0xa8 own sla+r has been received; ack has been returned load data byte or load data byte x x 0 0 1 1 0 1 last data byte will be transmitted and not ack should be received data byte will be transmitted and ack should be received 0xb0 arbitration lost in sla+r/w as master; own sla+r has been received; ack has been returned load data byte or load data byte x x 0 0 1 1 0 1 last data byte will be transmitted and not ack should be received data byte will be transmitted and ack should be received 0xb8 data byte in twdr has been transmitted; ack has been received load data byte or load data byte x x 0 0 1 1 0 1 last data byte will be transmitted and not ack should be received data byte will be transmitted and ack should be received 0xc0 data byte in twdr has been transmitted; not ack has been received no twdr action or no twdr action or no twdr action or no twdr action 0 0 1 1 0 0 0 0 1 1 1 1 0 1 0 1 switched to the not addressed slave mode; no recognition of own sla or gca switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1? switched to the not addressed slave mode; no recognition of own sla or gca; a start condition will be transmitted when the bus becomes free switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1?; a start condition will be transmitted when the bus becomes free 0xc8 last data byte in twdr has been transmitted (twea = ?0?); ack has been received no twdr action or no twdr action or no twdr action or no twdr action 0 0 1 1 0 0 0 0 1 1 1 1 0 1 0 1 switched to the not addressed slave mode; no recognition of own sla or gca switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1? switched to the not addressed slave mode; no recognition of own sla or gca; a start condition will be transmitted when the bus becomes free switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1?; a start condition will be transmitted when the bus becomes free atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 198 figure 21-18. formats and states in the slave transmitter mode 21.7.5 miscellaneous states there are two status code s that do not correspond to a defined twi state, see table 21-7 . status 0xf8 indicates that no relevant information is availabl e because the twint flag is not set. this occurs between other states, and when the twi is not involved in a serial transfer. status 0x00 indicates that a bus error has occurred during a 2- wire serial bus transfer. a bus error occurs when a start or stop condition occurs at an illegal position in the format fram e. examples of such illegal positions are during the serial transfer of an address byte, a data byte, or an acknowledge bit. when a bus error occurs, twin t is set. to recover from a bus error, the twsto flag must set and twint must be cleared by writing a logic one to it. this causes the twi to enter the not addressed slave mode and to clear the twsto flag (no ot her bits in twcr are affected). the sda and scl lines are released, and no stop condition is transmitted. s reception of the own slave address and one or more data bytes last data byte transmitted. switched to not adressed slave (twea = 0 a rbitration lost as master and addressed as slave from master to slave any number of data bytes and their associated acknowledge bits this number (contained in twsr) corresponds to a defined state of the two-wire serial bus. the prescaler bits are zero or masked to zero from slave to master sla r a data ap or s a data all 1s a data $a8 $b0 $b8 $c0 $c8 a p or s a n table 21-7. miscellaneous states status code (twsr) prescaler bits are 0 status of the 2-wire serial bus and 2-wire serial interface hardware application software response next action taken by twi hardware to/from twdr to twcr sta sto twint twea 0xf8 no relevant state information available; twint = ?0? no twdr action no twcr action wait or proceed current transfer 0x00 bus error due to an illegal start or stop condition no twdr action 0 1 1 x only the internal hardware is affected, no stop condition is sent on the bus. in all cases, the bus is released and twsto is cleared. 199 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 21.7.6 combining several twi modes in some cases, several twi modes must be combined in order to complete the desired action. consider for example reading data from a serial eeprom. ty pically, such a transfer involves the following steps: 1. the transfer must be initiated. 2. the eeprom must be instructed what location should be read. 3. the reading must be performed. 4. the transfer must be finished. note that data is transmitted both from master to slave and vice versa. the master must instru ct the slave what location it wants to read, requiring the use of the mt mode. subsequently, data must be read from the sl ave, implying the use of the mr mode. thus, the transfer direction must be changed. the mast er must keep control of the bus during al l these steps, and the steps should be carri ed out as an atomical operat ion. if this principle is violated in a multi ma ster system, another maste r can alter the data pointer in the eeprom between steps 2 and 3, and the master will read the wrong data location. such a change in transfer direction is accomplished by transmitti ng a repeated start between the transmission of the address byte and reception of the da ta. after a repeated start, the master keeps ownership of the bus. the following figure shows the flow in this transfer. figure 21-19. combining several tw i modes to access a serial eeprom 21.8 multi-master systems and arbitration if multiple masters are connec ted to the same bus, transmissions may be init iated simultaneously by one or more of them. the twi standard ensures that such situat ions are handled in such a way that one of the masters will be allowed to proceed with the transfer, and that no data will be lost in the process. an example of an arbi tration situation is depicted below, wher e two masters are trying to trans mit data to a slave receiver. figure 21-20. an arbitration example several different scenarios may arise dur ing arbitration, as described below: two or more masters are performing i dentical communication with the same slave. in this case, neither the slave nor any of the masters will know about the bus contention. two or more masters are accessing the same slave with differ ent data or direction bit. in this case, arbitration will occur, either in the read/write bit or in the data bits. the masters trying to output a one on sda while another master outputs a zero will lose the arbitration. losing master s will switch to not addressed slave mode or wait until the bus is free and transmit a new start condition, depending on application software action. s s = start p = stop r s = repeated start p r s a sla + w a a a address master transmitter transmitted from master to slave transmitted from slave to master master receiver data sla + r device 1 master transmitter sda scl v cc device n ........ r1 r2 device 2 master transmitter device 3 slave receiver atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 200 two or more masters are accessing different slaves. in this case, arbitration will occur in the sla bits. masters trying to output a one on sda while another master outputs a zero will lose the arbitration. masters losing arbitration in sla will switch to slave mode to check if they are being addre ssed by the winning master. if addressed, they will switch to sr or st mode, depending on the value of the read/write bit. if they are not being addressed, they will switch to not addressed slave mode or wait until the bus is free and transmit a new star t condition, depending on application software action. this is summarized in figure 21-21 . possible status values are given in circles. figure 21-21. possible status codes caused by arbitration 21.9 register description 21.9.1 twbr ? twi bi t rate register ? bits 7:0 ? twi bit rate register twbr selects the division factor for the bit rate generator. th e bit rate generator is a frequ ency divider which generates the scl clock frequency in the master modes. see section 21.5.2 ?bit rate generator unit? on page 182 for calculating bit rates. 21.9.2 twcr ? twi control register the twcr is used to control the operation of the twi. it is used to enable the twi, to initiate a master access by applying a start condition to the bus, to generate a receiver acknowledge , to generate a stop condition, and to control halting of the bus while the data to be written to the bus are written to the twdr. it also indica tes a write collision if data is attempted written to twdr while the register is inaccessible. own address/ general call received direction twi bus will be released and not addressed slave mode will be entered a start condition will be transmitted when the bus becomes free data byte will be received and not ack will be returned data byte will be received and ack will be returned last data byte will be transmitted and not ack should be received data byte will be transmitted and ack should be received start sla no yes write read 38 68/78 arbitration lost in sla arbitration lost in data data stop b0 bit 76543210 (0xb8) twbr7 twbr6 twbr5 twbr4 twbr3 twbr2 twbr1 twbr0 twbr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 (0xbc) twint twea twsta twsto twwc twen ?twietwcr read/write r/w r/w r/w r/w r r/w r r/w initial value00000000 201 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 ? bit 7 ? twint: twi interrupt flag this bit is set by hardware when the twi has finished its curr ent job and expects application software response. if the i-bit i n sreg and twie in twcr are set, the mcu will jump to the twi interrupt vector. while the twin t flag is set, the scl low period is stretched. the twint flag must be cleared by software by writing a logic one to it. note that this flag is not automatically cleared by hardware when execut ing the interrupt routine. also note that clearing this flag starts the operation of the twi, so all accesses to the twi address register (twar) , twi status register (twsr), and twi data register (twdr) must be complete before clearing this flag. ? bit 6 ? twea: twi enable acknowledge bit the twea bit controls the generation of the acknowledge pulse. if the twea bit is written to one, the ack pulse is generated on the twi bus if the following conditions are met: 1. the device?s own slave address has been received. 2. a general call has been received, while the twgce bit in the twar is set. 3. a data byte has been received in master receiver or slave receiver mode. by writing the twea bit to zero, the device can be virtually disconnected from the 2-wire serial bus temporarily. address recognition can then be resumed by writing the twea bit to one again. ? bit 5 ? twsta: twi start condition bit the application writes the twsta bit to one when it desires to become a master on the 2-wire serial bus. the twi hardware checks if the bus is avail able, and gener ates a start condition on the bus if it is free. however, if the bus is not free, the twi waits until a stop condition is detect ed, and then generates a new start cond ition to claim the bus master status. twsta must be cleared by software when the start condition has been transmitted. ? bit 4 ? twsto: twi stop condition bit writing the twsto bit to one in master mode will generate a stop condition on the 2-wire serial bus. when the stop condition is executed on the bus, the twsto bit is cleared automatically. in slav e mode, setting the twsto bit can be used to recover from an error condition. this will not generate a stop condition, but the twi returns to a well-defined unaddressed slave mode and releases the sc l and sda lines to a high impedance state. ? bit 3 ? twwc: twi write collision flag the twwc bit is set when attemp ting to write to the twi data register ? twdr when twint is low. this flag is cleared by writing the twdr register when twint is high. ? bit 2 ? twen: twi enable bit the twen bit enables twi operation and activates the twi interf ace. when twen is written to one, the twi takes control over the i/o pins connected to the scl and sda pins, enabling the slew-rate limiters and spike filt ers. if this bit is written to zero, the twi is swit ched off and all twi transmissions are termina ted, regardless of any ongoing operation. ? bit 1 ? reserved this bit is a reserved bit and will always read as zero. ? bit 0 ? twie: twi interrupt enable when this bit is written to one, and the i- bit in sreg is set, the twi interrupt r equest will be activated for as long as the twint flag is high. atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 202 21.9.3 twsr ? twi status register ? bits 7:3 ? tws: twi status these 5 bits reflect the status of the twi logic and the 2-wire serial bus. the different status codes are described section 21.7 ?transmission modes? on page 186 . note that the value read from twsr contains both the 5-bit status value and the 2-bit prescaler value. the application designer should mask the prescaler bits to zero when checking the status bits. this makes status checking independent of pre scaler setting. this approach is used in this datasheet, unless otherwise noted. ? bit 2 ? reserved this bit is reserved and will always read as zero. ? bits 1:0 ? twps: twi prescaler bits these bits can be read and written, and control the bit rate prescaler. to calculate bit rates, see section 21.5.2 ?bit rate generator unit? on page 182 . the value of twps1..0 is used in the equation. 21.9.4 twdr ? twi data register in transmit mode, twdr contains the nex t byte to be transmitted. in receive mo de, the twdr contains the last byte received. it is writable while the twi is not in the process of shifting a byte . this occurs when the twi interrupt flag (twint ) is set by hardware. note that the data register cannot be init ialized by the user before the fi rst interrupt occurs. the data i n twdr remains stable as long as twint is set. while data is shifted out, data on the bus is simultaneously shifted in. twdr always contains the last byte present on the bus, except a fter a wake up from a sleep mode by the twi interrupt. in this case, the contents of twdr is undefined. in the case of a lost bu s arbitration, no data is lost in the transition from master t o slave. handling of the ack bit is controlled automatically by the twi logic, the cpu cannot access the ack bit directly. ? bits 7:0 ? twd: twi data register these eight bits constitute the next data byte to be transmitte d, or the latest data byte received on the 2-wire serial bus. bit 76543210 (0xb9) tws7 tws6 tws5 tws4 tws3 ? twps1 twps0 twsr read/write rrrrrrr/wr/w initial value11111000 table 21-8. twi bit rate prescaler twps1 twps0 prescaler value 0 0 1 0 1 4 1 0 16 1 1 64 bit 76543210 (0xbb) twd7 twd6 twd5 twd4 twd3 twd2 twd1 twd0 twdr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value11111111 203 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 21.9.5 twar ? twi (slave) address register the twar should be loaded with the 7-bit slave address (in the seven most significant bits of twar) to which the twi will respond when programmed as a slave transmitter or receiver , and not needed in the master modes. in multi master systems, twar must be set in masters which c an be addressed as slaves by other masters. the lsb of twar is used to enable recognition of the general call address (0x00). there is an associated address comparator that looks for the slave address (or general call address if enabled) in the received serial address. if a match is found, an interrupt request is generated. ? bits 7:1 ? twa: twi (slave) address register these seven bits constitute the slave address of the twi unit. ? bit 0 ? twgce: twi general call recognition enable bit if set, this bit enables the recognition of a general call given over the 2-wire serial bus. 21.9.6 twamr ? twi (slave) address mask register ? bits 7:1 ? twam: twi address mask the twamr can be loaded with a 7-bit slave address mask. each of the bits in twamr can mask (disable) the corresponding address bit in the twi address register (twar). if the mask bit is set to one then the address match logic ignores the compare between the incoming address bit and the corresponding bit in twar. figure 21-22 shows the address match logic in detail. figure 21-22. twi address match logic, block diagram ? bit 0 ? reserved this bit is reserved and will always read as zero. bit 76543210 (0xba) twa6 twa5 twa4 twa3 twa2 twa1 twa0 twgce twar read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value11111110 bit 76543210 (0xbd) twam[6:0] ?twamr read/write r/w r/w r/w r/w r/w r/w r/w r initial value00000000 twar0 address match twamr0 address bit comparator 6 to 1 address bit comparator 0 address bit 0 atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 204 22. ac - analog comparator 22.1 overview the analog comparator compares the input values on the positive pin ain0 and negative pin ain1. when the voltage on the positive pin ain0 is higher than the vo ltage on the negative pin ain1, the analog comparator output, aco, is set. the comparator?s output can be set to trigger the timer/counter1 input capture function. in addition, the comparator can trigger a separate interrupt, exclusive to the analog co mparator. the user can select interrupt tr iggering on comparator output rise, fal l or toggle. a block diagram of the comparator and its surrounding logic is shown in figure 22-1 . the power reduction adc bit, pradc, in section 10.12.3 ?prr0 ? power r eduction register 0? on page 39 must be disabled by writing a logical zero to be able to use the adc input mux. figure 22-1. analog comparator block diagram (2) notes: 1. see table 22-1 on page 205 . 2. refer to figure 1-1 on page 3 and table 14-5 on page 64 for analog comparator pin placement. 22.2 analog comparator multiplexed input it is possible to select any of the adc7..0 pins to replace the negative input to the analog comparator. the adc multiplexer is used to select this input, and consequently, the adc must be switched off to utilize this f eature. if the analog comparator multiplexer enable bit (acme in adcsrb) is set and the adc is switched off (aden in adcsra is zero), mux2..0 in admux select the input pin to replace the negativ e input to the analog comparator, as shown in table 22-1 on page 205 . if acme is cleared or aden is set, ain1 is applie d to the negative input to the analog comparator. bandgap reference interrupt select ain0 vcc acis1 adc multiplexer output (1) acis0 acic aco acie analog comparator irq aci to t/c1 capture trigger mux acbg acme aden acd + - ain1 205 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 22.3 register description 22.3.1 adcsrb ? adc control and status register b ? bit 6 ? acme: analog comparator multiplexer enable when this bit is written logic one and the adc is switched of f (aden in adcsra is zero), the adc multiplexer selects the negative input to the analog comparator. when this bit is written logic zero, ain1 is applied to the negative input of the analog comparator. for a detailed description of this bit, see section 22.2 ?analog comparator multiplexed input? on page 204 . 22.3.2 acsr ? analog comparator control and status register ? bit 7 ? acd: analog comparator disable when this bit is written logic one, the power to the analog compar ator is switched off. this bit can be set at any time to turn off the analog comparator. this will reduce power consumption in active and idle mode. when changing the acd bit, the analog comparator interrupt must be disabled by clearing the acie bit in acsr. otherwise an interrupt can occur when the bit is changed. ? bit 6 ? acbg: analog comparator bandgap select when this bit is set, a fixed bandgap reference voltage replaces the positive input to the analog comparator. when this bit is cleared, ain0 is applied to the positive in put of the analog comparator. when bandga p reference is used as input to the analog comparator, it will take a certain time for the voltage to stabilize. if not stabilized, the first conversion may give w rong value. see section 11.2 ?internal voltage reference? on page 43 . ? bit 5 ? aco: analog comparator output the output of the analog compar ator is synchronized and then di rectly connected to aco. the synchronization introduces a delay of 1 - 2 clock cycles. table 22-1. analog comparator mulitiplexed input acme aden mux2..0 analog comparator negative input 0 x xxx ain1 1 1 xxx ain1 1 0 000 adc0 1 0 001 adc1 1 0 010 adc2 1 0 011 adc3 1 0 100 adc4 1 0 101 adc5 1 0 110 adc6 1 0 111 adc7 bit 7 6543210 (0x7b) ? acme ? ? - adts2 adts1 adts0 adcsrb read/write r r/w r r r r/w r/w r/w initial value0 0000000 bit 76543210 0x30 (0x50) acd acbg aco aci acie acic acis1 acis0 acsr read/write r/w r/w r r/w r/w r/w r/w r/w initial value00n/a00000 atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 206 ? bit 4 ? aci: analog comparator interrupt flag this bit is set by hardware when a comparator output event triggers the interrupt mode defined by acis1 and acis0. the analog comparator interrupt routine is execut ed if the acie bit is set and the i-bit in sreg is set. aci is cleared by hardware when executing the corresponding interrupt handling vector. alter natively, aci is cleared by writing a logic one to the flag. ? bit 3 ? acie: analog comparator interrupt enable when the acie bit is written logic one and the i-bit in the stat us register is set, the analog comparator interrupt is activate d. when written logic zero, the interrupt is disabled. ? bit 2 ? acic: analog comparator input capture enable when written logic one, this bit enables the input capture function in timer/counter1 to be triggered by the analog comparator. the comparator out put is in this case directly connected to the input capture front- end logic, making the comparator utilize the noise c anceler and edge select features of the timer/ counter1 input capture interrupt. when written logic zero, no connection between the analog comparator and t he input capture function exists. to make the comparator trigger the timer/counter1 input capture in terrupt, the icie1 bit in th e timer interrupt mask register (timsk1) must be set. ? bits 1:0 ? acis1:acis0: analog comparator interrupt mode select these bits determine which comparator events that trigger th e analog comparator interrupt. the different settings are shown in table 22-2 . when changing the acis1/acis0 bits, the a nalog comparator interrupt must be disabl ed by clearing its interrupt enable bit in the acsr register. otherwise an inte rrupt can occur when the bits are changed. 22.3.3 didr1 ? digital input disable register 1 ? bit 1:0 ? ain1d:ain0d: ain1 :ain0 digital input disable when this bit is written logic one, the digital input buffer on the ain1/0 pin is disabled. the corresponding pin register bit will always read as zero when this bit is set. when an analog signal is applied to the ain1/0 pin and the digital input from this pi n is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer. table 22-2. acis1/acis0 settings acis1 acis0 interrupt mode 0 0 comparator interr upt on output toggle. 0 1 reserved 1 0 comparator interrupt on falling output edge. 1 1 comparator interrupt on rising output edge. bit 76543210 (0x7f) ? ? ? ? ? ? ain1d ain0d didr1 read/write rrrrrrr/wr/w initial value00000000 207 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 23. adc - analog-to-digital converter 23.1 features 10-bit resolution 0.5 lsb integral non-linearity 2 lsb absolute accuracy 65 - 260s conversion time up to 15ksps at maximum resolution 8 multiplexed single ended input channels differential mode with selectable gain at 1x, 10x or 200x optional left adjustment for adc result readout 0 - v cc adc input voltage range 2.7 - v cc differential adc voltage range selectable 2.56v or 1.1v adc reference voltage free running or single conversion mode adc start conversion by auto triggering on interrupt sources interrupt on adc conversion complete sleep mode noise canceler 23.2 overview the atmel ? atmega164p-b/324p-b/644p-b features a 10-bit successive approximat ion adc. the adc is connected to an 8-channel analog multiplexer which allows 8 single-ended voltage inputs constructed fr om the pins of port a. the single-ended voltage inputs refer to 0v (gnd). the device also supports 16 differential voltage input combinat ions. two of the differential inputs (adc1, adc0 and adc3, adc2) are equipped with a programmable gain stag e. this provides amplification steps of 0 db (1x), 20 db (10x), or 46 db (200x) on the differential input voltage before the a/d conver sion. seven differential analog input channels share a common negative terminal (adc1), while any other adc input can be selected as the positive input terminal. if 1x or 10x gain is used, 8-bit resolution can be expected. if 200x gain is used, 6-bit reso lution can be expected. note that internal references of 1.1v should not be used on 10x and 200x gain. the adc contains a sample and hold circuit which ensures that the input voltage to the adc is held at a constant level during conversion. a block diagram of the adc is shown in figure 23-1 on page 208 . the adc has a separate analog supply voltage pin, avc c. avcc must not differ mo re than 0.3 v from v cc . see the section 23.7 ?adc noise canceler? on page 214 on how to connect this pin. internal reference voltages of nomina lly 1.1v, 2.56v or avcc ar e provided on-chip. the voltage reference may be externally decoupled at the aref pin by a capacitor for better noise performance. atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 208 figure 23-1. analog-to-digital converter block schematic prescaler start - + 15 0 adc multiplexer select (admux) trigger select mux decoder avcc adts[2:0] interrupt flags aref 10-bit dac gain amplifier sample and hold comparator neg input mux internal reference (1.1v/2.56v) conversion logic adc ctrl and status register b (adcsrb) adc conversion complete irq adc ctrl and status register a (adcsra) adc data register (adch/adcl) - + adif aden channel selection dif/ gain select adif mux[4:0] refs[1:0] adc[2:0] adlar adsc adate adie pos input mux adps[2:0] adc[9:0] adc[7:09 gnd bandgap reference (1.1v) adc multiplexer output 209 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 23.3 operation the adc converts an analog input voltage to a 10-bit digital value through successive approximation. the minimum value represents gnd and the maximum value represents the volta ge on the aref pin minus 1 lsb. optionally, avcc or an internal 2.56v reference voltage may be connected to the aref pin by writing to the refsn bits in the admux register. the internal voltage reference may thus be decoupled by an external capacitor at the aref pin to improve noise immunity. the analog input channel and differential ga in are selected by writing to the mux bits in admux. any of the adc input pins, as well as gnd and a fixed bandgap voltage reference, can be selected as single ended inputs to the adc. a selection of adc input pins can be selected as positive and negative inputs to the differential gain amplifier. if differential channels are selected, the differential gain stage amplifies the voltage difference between the selected input channel pair by the selected gain factor. this amplified va lue then becomes the analog input to the adc. if single ended channels are used, the gain amp lifier is bypassed altogether. the adc is enabled by setting the adc enable bit, aden in adcsra. voltage reference and input channel selections will not go into effect until aden is set. the adc does not cons ume power when aden is cleared, so it is recommended to switch off the adc before entering power saving sleep modes. the adc generates a 10-bit result which is presented in the adc data registers, adch and adcl. by default, the result is presented right adjusted, but can optionally be presen ted left adjusted by setting the adlar bit in admux. if the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read adch. otherwise, adcl mus t be read first, then adch, to ensure that the content of the data registers belongs to the same conversion. once adcl is read, adc access to data registers is blocked. this means t hat if adcl has been read, and a conversion completes before adch is read, neither register is updated and the result from the conversion is lost. when adch is read, adc access to the adch and adcl registers is re-enabled. the adc has its own interrupt which can be triggered when a conversion completes. when adc access to the data registers is prohibited between reading of ad ch and adcl, the interrupt will trigger even if the result is lost. 23.4 starting a conversion a single conversion is started by writing a logical one to the a dc start conversion bit, adsc. this bit stays high as long as the conversion is in progress and will be cleared by hardware w hen the conversion is completed. if a different data channel is selected while a conversion is in pr ogress, the adc will finish the current conversion before performing the channel change. alternatively, a conversion can be triggered automatically by various sources. auto triggering is enabled by setting the adc auto trigger enable bit, adate in adcsra. the trigger source is selected by setting the adc trigger select bits, adts in adcsrb (see description of the adts bits for a list of the trigger sources). when a positive edge occurs on the selected trigger signal, the adc prescaler is reset and a conversion is star ted. this provides a method of starting conversions at fixed intervals. if the trigger signal still is set when the conversion comp letes, a new conversion will not be started. if another positive edge occurs on the trigger signal dur ing conversion, the edge will be ignored. no te that an interrupt flag will be set even if the specific interrupt is disabled or the global interrupt enable bit in sreg is cleared. a conversion can thus be triggered without causing an interr upt. however, the interrupt flag must be cleared in order to trigger a new conversion at the next interrupt event. figure 23-2. adc au to trigger logic edge detector conversion logic prescaler adif adsc adate start clk adc adts[2:0] . . . . source 1 source n atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 210 using the adc interrupt flag as a trigger source makes the a dc start a new conversion as soon as the ongoing conversion has finished. the adc then operates in free running mode, constant ly sampling and updating the adc data register. the first conversion must be started by writing a logical one to the adsc bit in adcsra. in this mode the adc will perform successive conversions independently of whether t he adc interrupt flag, adif is cleared or not. if auto triggering is enabled, single conv ersions can be started by writing adsc in adcsra to one. adsc can also be used to determine if a conversion is in progress. the adsc bit wi ll be read as one during a conv ersion, independently of how the conversion was started. 23.5 prescaling and conversion timing figure 23-3. adc prescaler by default, the successive approximation circuitry requires an input clock frequency between 50khz and 200khz to get maximum resolution. if a lower resolution than 10 bits is needed, the input clock frequency to the adc can be higher than 200khz to get a higher sample rate. the adc module contains a prescaler, which generates an acceptable adc clock frequency from any cpu frequency above 100khz. the prescaling is set by the adps bits in adcsra. the prescaler starts counting from the moment the adc is switched on by setting the aden bit in adcsra. the prescaler keeps running for as long as the aden bit is set, and is continuously reset when aden is low. when initiating a single ended conversion by setting the adsc bi t in adcsra, the conversion starts at the following rising edge of the adc clock cycle. see section 23.5.1 ?differential gain channels? on page 213 for details on differential conversion timing. a normal conversion takes 13 adc clock cycles . the first conversion after the adc is switched on (aden in adcsra is set) takes 25 adc clock cycles in order to initialize the analog circuitry. when the bandgap reference voltage is used as input to the adc, it will ta ke a certain time for the voltage to stabilize. if no t stabilized, the first value read after the first conversion may be wrong. the actual sample-and-hold takes place 1.5 adc clock cycles after the start of a normal conversion and 13.5 adc clock cycles after the start of a first conversion. when a conversion is complete, the result is written to the adc data registers, a nd adif is set. in single conversion mode, adsc is cleared simu ltaneously. the software may then set adsc again, and a new conversion will be initiated on the first rising adc clock edge. when auto triggering is used, the prescaler is reset when the trigger event occurs. this assures a fixed delay from the trigger event to the start of conversion. in this mode, the sample-a nd-hold takes place 2 adc clock cycles after the rising edge on the trigger source signal. thre e additional cpu clock cycles ar e used for synchronization logic. when using differential mode, along wit h auto trigging from a source other than the adc conversion complete, each conversion will require 25 adc clocks. this is because the adc must be disabled and re-enabled after every conversion. in free running mode, a new conversion w ill be started immediately after the conversion completes, while adsc remains high. for a summary of conversion times, see table 23-1 on page 212 . 7-bit adc prescaler adc clock source aden start ck adps0 adps1 adps2 reset ck/2 ck/4 ck/8 ck/16 ck/32 ck/64 ck/128 211 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 figure 23-4. adc timing di agram, first conversion (single conversion mode) figure 23-5. adc timing diag ram, single conversion 1 2 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 2 3 cycle number first conversion msb of result lsb of result next conversion mux and refs update conversion complete mux and refs update adc clock aden adsc adif adch adcl sample and hold 12345678910111213 123 cycle number one conversion msb of result lsb of result next conversion mux and refs update conversion complete mux and refs update adc clock adsc adif adch adcl sample and hold atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 212 figure 23-6. adc timing diagram, auto triggered conversion figure 23-7. adc timi ng diagram, free running conversion table 23-1. adc co nversion time condition sample and hold (cycles from start of conversion) conversion time (cycles) first conversion 14.5 25 normal conversions, single ended 1.5 13 auto triggered conversions 2 13.5 normal conversions, differential 1.5/2.5 13/14 12345678910111213 12 cycle number one conversion msb of result lsb of result next conversion mux and refs update prescaler reset prescale r reset conversion complete adc clock trigger source adif adate adch adcl sample and hold 11 12 13 1 2 3 4 cycle number one conversion msb of result lsb of result next conversion mux and refs update conversion complete adc clock adsc adif adch adcl sample and hold 213 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 23.5.1 differential gain channels when using differential gain channels, certain aspects of the conversion need to be taken into consideration. note that the differential channels should not be used with an aref < 2v. differential conversions are synchronized to the internal clock ck adc2 equal to half the adc clock. this synchronization is done automatically by the adc interface in such a way that the sample-a nd-hold occurs at a specific phase of ck adc2 . a conversion initiated by the user (i.e., all single conv ersions, and the first free running conversion) when ck adc2 is low will take the same amount of time as a single ended conversion (13 adc clock cycles from the next prescaled clock cycle). a conversion initiated by the user when ck adc2 is high will take 14 adc clock cycles due to the synchronizati on mechanism. in free running mode, a new conversion is initiated immediat ely after the previous conversion completes, and since ck adc2 is high at this time, all automatically started (i.e., all but the first) free running conversions will take 14 adc clock cycles. the gain stage is optimized for a bandwidth of 4khz at all gain settings. higher frequencies may be subjected to non-linear amplification. an external low-pass filter should be used if the input signal contains higher frequency components than the gain stage bandwidth. note that the adc clock frequency is independent of the gain stage bandwidth limitation. for example, the adc clock period may be 6s, allowing a channel to be sampled at 12ksps, regardless of the bandwidth of this channel. if differential gain channels are used and conversions are started by auto triggerin g, the adc must be switched off between conversions. when auto triggering is used, the adc prescaler is reset before the conversion is started. since the gain stage is dependent of a stable adc clock prior to the conversion , this conversion will not be valid. by disabling and then re-enabling the adc between each conversion (writing aden in adcsra to ?0? then to ?1?), only extended conversions are performed. the result from the extended conversions will be valid. see section 23.5 ?prescaling and conversion timing? on page 210 for timing details. 23.6 changing channel or reference selection the muxn and refs1:0 bits in the admux register are singl e buffered through a temporary register to which the cpu has random access. this ensures that the channels and referenc e selection only takes place at a safe point during the conversion. the channel and reference select ion is continuously updated until a conv ersion is started. once the conversion starts, the channel and reference selection is locked to ensure a sufficient sampling time for the adc. continuous updating resumes in the last adc clock cycle before the conversion completes (adif in adcsra is set). note that the conversion starts on the following rising adc clock edge after adsc is wri tten. the user is thus advised not to write new channel or reference selection values to admux until one adc clock cycle after adsc is written. if auto triggering is used, the exact time of the triggering event can be indetermin istic. special care must be taken when updating the admux register, in order to control wh ich conversion will be affected by the new settings. if both adate and aden is written to one, an interrupt event ca n occur at any time. if the admux register is changed in this period, the user cannot tell if the next conversion is based on the old or the new settings. admux can be safely updated in the following ways: 1. when adate or aden is cleared. 2. during conversion, minimum one a dc clock cycle after the trigger event. 3. after a conversion, before the interrupt flag used as trigger source is cleared. when updating admux in one of these conditions, the new settings will affect the next adc conversion. special care should be taken when changing differential channel s. once a differential channel has been selected, the gain stage may take as much as 125s to stabilize to the new value. thus conversions should not be started within the first 125s after selecting a new differential channel . alternatively, conversion results obta ined within this period should be discarded. the same settling time should be observed for the first differential conversion after changing adc reference (by changing the refs1:0 bits in admux). atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 214 23.6.1 adc input channels when changing channel selections, the user should observe the following guidelines to ensure that the correct channel is selected: in single conversion mode, always select the channel before starting the conversion. the channel selection may be changed one adc clock cycle after writing one to adsc. however, the simp lest method is to wait fo r the conversion to complete before changing the channel selection. in free running mode, always select the ch annel before starting the first conversion. the channel selection may be changed one adc clock cycle after writing one to adsc. however, the simp lest method is to wait for the first conversion to complete, and then change the channel selection. si nce the next conversion has already star ted automatically, the next result will reflect the previous channel selection. subsequent conversions will reflect the new channel selection. when switching to a differential gain channel, the first conv ersion result may have a poor accuracy due to the required settling time for the automatic offset canc ellation circuitry. the user should pref erably disregard the first conversion result . 23.6.2 adc voltage reference the reference voltage for the adc (v ref ) indicates the conversion range for the adc. single ended channels that exceed v ref will result in codes close to 0x3ff. v ref can be selected as either avcc, internal 2.56v reference, or external aref pin. avcc is connected to the adc through a passive switch. the internal 2.56v reference is generated from the internal bandgap reference (v bg ) through an internal amplifier. in either case, t he external aref pin is directly connected to the adc, and the reference voltage can be m ade more immune to noise by connecting a capacitor between the aref pin and ground. v ref can also be measured at the aref pin with a high impedant voltmeter. note that v ref is a high impedant source, and only a capacitive load should be connected in a system. if the user has a fixed voltage source connected to the aref pin, the user may not use the other reference voltage options in the application, as they will be shorte d to the external voltage. if no external voltage is applied to the aref pin, the use r may switch between avcc and 2.56v as reference selection. the first adc conversion result after switching reference voltage source may be inaccurate, and the us er is advised to discard this result. if differential channels are used, the selected refer ence should not be closer to avcc than indicated in table 28-10 on page 295 . 23.7 adc noise canceler the adc features a noise canceler that enables conversion during sleep mode to reduce noise induced from the cpu core and other i/o peripherals. the noise canceler can be used with adc noise reduction and idle mode. to make use of this feature, the following procedure should be used: 1. make sure that the adc is enabled and is not busy co nverting. single conversion mode must be selected and the adc conversion complete interrupt must be enabled. 2. enter adc noise reduction mode (or idle mode). the ad c will start a conversion once the cpu has been halted. 3. if no other interrupts occur before t he adc conversion completes, the adc interrupt will wake up the cpu and execute the adc conversion complete interrupt routine. if another inte rrupt wakes up the cpu before the adc conversion is complete, that interrupt will be executed, an d an adc conversion complete interrupt request will be generated when the adc conversion completes. the cpu wi ll remain in active mode until a new sleep command is executed. note that the adc will not be automatically turned off when entering ot her sleep modes than idle mode and adc noise reduction mode. the user is advised to write zero to aden before entering such sleep modes to avoid excessive power consumption. if the adc is enabled in su ch sleep modes and the user wants to perfor m differential conversions, the user is advised to switch the adc off and on af ter waking up from sleep to prompt an ex tended conversion to get a valid result. 215 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 23.7.1 analog in put circuitry the analog input circuitry for single ended channels is illustrated in figure 23-8 an analog source applied to adcn is subjected to the pin capacitance and input l eakage of that pin, regardless of whether t hat channel is selected as input for the adc. when the channel is selected, t he source must drive the s/h capacitor through the series resistance (combined resistance in the input path). the adc is optimized for analog signals wi th an output impedance of approximately 10k or less. if such a source is used, the sampling time will be negligible. if a source with higher impedance is used, the sampling time will depend on how long time the source needs to charge the s/h capacitor, with can vary widely. the user is recommended to only use low impedant sources with slowly varying signals, since this minimize s the required charge transfer to the s/h capacitor. if differential gain channels are used, the input circuitry lo oks somewhat different, although source impedances of a few hundred k or less is recommended. signal components higher than the nyquist frequency (f adc /2) should not be present for either kind of channels, to avoid distortion from unpredictable signal convol ution. the user is advised to remove high frequency components with a low-pass filter before applying the signals as inputs to the adc. figure 23-8. analog input circuitry 23.7.2 analog noise canceling techniques digital circuitry inside and outside the device generates emi which might affect the accuracy of analog measurements. if conversion accuracy is critical, the noise level can be reduced by applying the following techniques: i il v cc /2 c s/h = 14pf i ih a dcn 1 to 100k atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 216 1. keep analog signal paths as short as possible. make sure analog tra cks run over the analog ground plane, and keep them well away from high-speed switching digital tracks. 2. the avcc pin on the device should be connected to the digital v cc supply voltage via an lc network as shown in figure 23-9 . 3. use the adc noise canceler function to reduce induced noise from the cpu. 4. if any adc port pins are used as digi tal outputs, it is essential that th ese do not switch while a conversion is in progress. figure 23-9. adc power connections 23.7.3 offset comp ensation schemes the gain stage has a built-in offset cance llation circuitry that nulls the offset of differential measurements as much as possible. the remaining offset in the analog path can be me asured directly by selecting the same channel for both differential inputs. this offset residue c an be then subtracted in software from th e measurement results. using this kind of software based offset correction, offset on any channel can be reduced below one lsb. 23.7.4 adc accura cy definitions an n-bit single-ended adc converts a voltage linearly between gnd and v ref in 2 n steps (lsbs). the lowest code is read as 0, and the highest code is read as 2 n -1. gnd vcc pa0 (adc0) pa1 (adc1) pa2 (adc2) pa3 (adc3) pa4 (adc4) analog ground plane pa5 (adc5) pa6 (adc6) pa7 (adc7) aref gnd 100nf 10h avcc pc7 217 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 several parameters describe the deviation from the ideal behavior: offset: the deviation of the fi rst transition (0x000 to 0x001) compared to t he ideal transition (at 0.5 lsb). ideal value: 0 lsb. figure 23-10. offset error gain error: after adjusting for offset, the gain error is foun d as the deviation of the last transition (0x3fe to 0x3ff) compared to the ideal transition (at 1.5 lsb below maximum). ideal value: 0 lsb figure 23-11. gain error offset error output code ideal adc actual adc v ref input voltage output code ideal adc actual adc v ref input voltage gain error atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 218 integral non-linearity (inl): after adju sting for offset and gain error, the in l is the maximum deviation of an actual transition compared to an ideal transition for any code. ideal value: 0 lsb. figure 23-12. integral non-linearity (inl) differential non-linearity (dnl): the maxi mum deviation of the actual code widt h (the interval between two adjacent transitions) from the ideal code width (1 lsb). ideal value: 0 lsb. figure 23-13. differential non-linearity (dnl) quantization error: due to the quantization of the input voltage into a fini te number of codes, a range of input voltages (1 lsb wide) will code to the same value. always 0.5 lsb. absolute accuracy: the maximum deviation of an actual (unadjusted) transition compared to an ideal transition for any code. this is the compound effect of offset, gain error, di fferential error, non-linearity, and quantization error. ideal value: 0.5 lsb. output code ideal adc inl actual adc v ref input voltage output code 0x3ff 0x000 0 1 lsb dnl v ref input voltage 219 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 23.8 adc conversion result after the conversion is complete (adif is high), the conversi on result can be found in the adc result registers (adcl, adch). for single ended conversion, the result is where v in is the voltage on the selected input pin and v ref the selected voltage reference (see table 23-3 on page 220 and table 23-4 on page 221 ). 0x000 represents analog ground, and 0x3ff represents the select ed reference voltage minus one lsb. if differential channels are used, the result is where v pos is the voltage on the positive input pin, v neg the voltage on the negative input pin, gain the selected gain factor, and v ref the selected voltage reference. the result is presen ted in two?s complement form, from 0x200 (-512d) through 0x1ff (+511d). note that if the user wants to perform a quick polar ity check of the results, it is sufficient to read the msb o f the result (adc9 in adch). if this bit is one, the result is negative, and if this bit is zero, the result is positive. figure 23-14 shows the decoding of the differential input range. table 23-2 on page 220 shows the resulting output codes if the different ial input channel pair (adcn - adcm) is selected with a gain of gain and a reference voltage of v ref . figure 23-14. differential measurement range adc v in 1024 ? v ref ------------------------- = adc v pos v neg ? () gain 512 ?? v ref ----------------------------------------------------------------------- = output code 0x1ff 0x000 0 0x3ff 0x200 v ref /gain v ref /gain differential input voltage (volts) atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 220 example: admux = 0xed (adc3 - adc2, 10x gain, 2. 56v reference, left adjusted result) voltage on adc3 is 300mv, voltage on adc2 is 500mv. adcr = 512 10 (300 ? 500) / 2560 = ?400 = 0x270 adcl will thus read 0x00, and adch will read 0x9c. writ ing zero to adlar right adjusts the result: adcl = 0x70, adch = 0x02. 23.9 register description 23.9.1 admux ? adc multiple xer selectio n register ? bit 7:6 ? refs1:0: reference selection bits these bits select the voltage reference for the adc, as shown in table 23-3 . if these bits are changed during a conversion, the change will not go in effect until this conversion is comple te (adif in adcsra is set). the internal voltage reference options may not be used if an external refer ence voltage is being applied to the aref pin. ? bit 5 ? adlar: adc left adjust result the adlar bit affects the presentation of the adc conversion result in the adc data register. write one to adlar to left adjust the result. otherwise, the result is right adjusted. changing the adla r bit will affect the adc data register immediately, regardless of any ongoing conversions. for a complete description of this bit, see section 23.9.3 ?adcl and adch ? the adc data register? on page 223 . table 23-2. correlation between in put voltage and output codes v adcn read code corresponding decimal value v adcm + v ref /gain 0x1ff 511 v adcm + 0.999 v ref /gain 0x1ff 511 v adcm + 0.998 v ref /gain 0x1fe 510 ... ... ... v adcm + 0.001 v ref /gain 0x001 1 v adcm 0x000 0 v adcm ? 0.001 v ref /gain 0x3ff -1 ... ... ... v adcm ? 0.999 v ref /gain 0x201 ?511 v adcm ? v ref /gain 0x200 ?512 bit 76543210 (0x7c) refs1 refs0 adlar mux4 mux3 mux2 mux1 mux0 admux read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 table 23-3. voltage reference selections for adc refs1 refs0 voltage reference selection 0 0 aref, internal v ref turned off 0 1 avcc with external capacitor at aref pin 1 0 internal 1.1v voltage reference with external capacitor at aref pin 1 1 internal 2.56v voltage reference with external capacitor at aref pin note: if differential channels are selected, only 2. 56v should be used as internal voltage reference. 221 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 ? bits 4:0 ? mux4:0: analog channel and gain selection bits the value of these bits selects which comb ination of analog inputs are conn ected to the adc. these bits also select the gain for the differential channels. see table 23-4 on page 221 for details. if these bits ar e changed during a conversion, the change will not go in effect until this conversi on is complete (adif in adcsra is set). table 23-4. input channel and gain selections mux4..0 single ended input positive differential input negative differential input gain 00000 adc0 n/a 00001 adc1 00010 adc2 00011 adc3 00100 adc4 00101 adc5 00110 adc6 00111 adc7 01000 n/a adc0 adc0 10x 01001 adc1 adc0 10x 01010 adc0 adc0 200x 01011 adc1 adc0 200x 01100 adc2 adc2 10x 01101 adc3 adc2 10x 01110 adc2 adc2 200x 01111 adc3 adc2 200x 10000 adc0 adc1 1x 10001 adc1 adc1 1x 10010 adc2 adc1 1x 10011 adc3 adc1 1x 10100 adc4 adc1 1x 10101 adc5 adc1 1x 10110 adc6 adc1 1x 10111 adc7 adc1 1x 11000 adc0 adc2 1x 11001 adc1 adc2 1x 11010 adc2 adc2 1x 11011 adc3 adc2 1x 11100 adc4 adc2 1x 11101 adc5 adc2 1x 11110 1.1v (v bg ) n/a 11111 0 v (gnd) atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 222 23.9.2 adcsra ? adc control and status register a ? bit 7 ? aden: adc enable writing this bit to one enables the adc. by writing it to zero, the adc is turned o ff. turning the adc off while a conversion i s in progress, will terminate this conversion. ? bit 6 ? adsc: adc start conversion in single conversion mode, write this bit to one to start each conversion. in free runni ng mode, write this bit to one to start the first conversion. the first conversion after adsc has been writt en after the adc has been enabled, or if adsc is written at the same time as the adc is enabled, will take 25 adc clock cycles instead of the normal 13. this first conversion performs initialization of the adc. adsc will read as one as long as a conversion is in progress. when the conversion is complete, it returns to zero. writing zero to this bit has no effect. ? bit 5 ? adate: adc auto trigger enable when this bit is written to one, auto tr iggering of the adc is enabled . the adc will start a conversion on a positive edge of the selected trigger signal. the trigger s ource is selected by setting the adc trigger select bits, adts in adcsrb. ? bit 4 ? adif: adc interrupt flag this bit is set when an adc conversion completes and th e data registers are updated. the adc conversion complete interrupt is executed if the adie bit and the i-bit in sreg are set. adif is cleared by hardware when executing the corresponding interrupt handling vector. alter natively, adif is cleared by writing a logical one to the flag. beware that if doing a read-modify-write on adcsra, a pending interrupt can be di sabled. this also applies if the sbi and cbi instructions are used. ? bit 3 ? adie: adc interrupt enable when this bit is written to one and the i-bit in sreg is set, the adc conversion comp lete interrupt is activated. ? bits 2:0 ? adps2:0: adc prescaler select bits these bits determine the division factor between the xtal frequency and the input clock to the adc. bit 76543210 (0x7a) aden adsc adate adif adie adps2 adps1 adps0 adcsra read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 table 23-5. adc prescaler selections adps2 adps1 adps0 division factor 0 0 0 2 0 0 1 2 0 1 0 4 0 1 1 8 1 0 0 16 1 0 1 32 1 1 0 64 1 1 1 128 223 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 23.9.3 adcl and adch ? the adc data register 23.9.3.1 adlar = 0 23.9.3.2 adlar = 1 when an adc conversion is complete, the result is found in thes e two registers. if differential channels are used, the result i s presented in two?s complement form. when adcl is read, the adc data register is not updated until adch is read. consequ ently, if the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read adch. otherwis e, adcl must be read first, then adch. the adlar bit in admux, and the muxn bits in admux affect the way the result is read from the registers. if adlar is set, the result is left adjusted. if adlar is clea red (default), the resu lt is right adjusted. ? adc9:0: adc conversion result these bits represent the result fr om the conversion, as detailed in section 23.8 ?adc conversion result? on page 219 . 23.9.4 adcsrb ? adc control and status register b ? bit 7, 5:3 ? reserved these bits are reserved for future use in the atmel ? atmega164p-b/324p-b/644p-b. for ensuring culpability with future devices, these bits must be writt en zero when adcsrb is written. bit 151413121110 9 8 (0x79) ? ? ? ? ? ? adc9 adc8 adch (0x78) adc7 adc6 adc5 adc4 adc3 adc2 adc1 adc0 adcl 76543210 read/writerrrrrrrr rrrrrrrr initial value00000000 00000000 bit 151413121110 9 8 (0x79) adc9 adc8 adc7 adc6 adc5 adc4 adc3 adc2 adch (0x78) adc1 adc0 ? ? ? ? ? ? adcl 76543210 read/writerrrrrrrr rrrrrrrr initial value00000000 00000000 bit 765 4 3210 (0x7b) ? acme ? ? ? adts2 adts1 adts0 adcsrb read/write r r/w r r r r/w r/w r/w initial value 0 0 0 0 0 0 0 0 atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 224 ? bit 2:0 ? adts2:0: adc auto trigger source if adate in adcsra is written to one, t he value of these bits selects which source will trigger an adc conversion. if adate is cleared, the adts[2:0] settings will hav e no effect. a conversion will be trigger ed by the rising edge of the selected interrupt flag. note that switching from a trigger source that is cleared to a trigger source that is set, will generate a posi tive edge on the trigger signal. if aden in adcsra is set, this will start a conversion. switching to free running mode (adts[2:0]=0) will not cause a trigger even t, even if the adc interrupt flag is set. 23.9.5 didr0 ? digital input disable register 0 ? bit 7:0 ? adc7d..adc0d: adc7:0 digital input disable when this bit is written logic one, the digital input buffer on the corresponding adc pin is disabled. the corresponding pin register bit will always read as zero when this bit is set. wh en an analog signal is applied to the adc7:0 pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer . table 23-6. adc auto trig ger source selections adts2 adts1 adts0 trigger source 0 0 0 free running mode 0 0 1 analog comparator 0 1 0 external interrupt request 0 0 1 1 timer/counter0 compare match 1 0 0 timer/counter0 overflow 1 0 1 timer/counter1 compare match b 1 1 0 timer/counter1 overflow 1 1 1 timer/counter1 capture event bit 76543210 (0x7e) adc7d adc6d adc5d adc4d adc3d adc2d adc1d adc0d didr0 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 225 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 24. jtag interface and on-chip debug system 24.1 features jtag (ieee std. 1149.1 compliant) interface boundary-scan capabilities according to the ieee std. 1149.1 (jtag) standard debugger access to: all internal peripheral units internal and external ram the internal register file program counter eeprom and flash memories extensive on-chip debug support for break conditions, including avr ? break instruction break on change of program memory flow single step break program memory break points on single address or address range data memory break points on single address or address range programming of flash, eeprom, fuses, and lock bits through the jtag interface on-chip debugging supported by avr studio ? 24.2 overview the avr ieee std. 1149.1 compliant jtag interface can be used for testing pcbs by using the jtag boundary-scan capability programming the non-volatile memories, fuses and lock bits on-chip debugging a brief description is given in the following sections. detailed descriptions for programming via the jtag interface, and using the boundary-scan chain can be found in the sections section 27.10 ?programming via the jtag interface? on page 274 and section 25. ?ieee 1149.1 (jtag) boundary-scan? on page 231 , respectively. the on-chip debug support is considered being private jtag instructions, and di stributed within atmel and to selected third party vendors only. figure 24-1 on page 226 shows a block diagram of the jtag interface and the on-chip debug system. the tap controller is a state machine controlled by the tck and tms signals. the tap controller selects either the jtag instruction register or one of several data registers as the scan chain (shift regi ster) between the tdi ? input and tdo ? output. the instruction register holds jtag instructions cont rolling the behavior of a data register. the id-register, bypass register, and the boundary-scan chain are the data registers used for board-level testing. the jtag programming interface (actually consisting of several physical and virtual data registers) is used for serial programming via the jtag interface. the internal scan chain and break point scan chain are used for on-chip debugging only. atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 226 24.3 tap ? test access port the jtag interface is accessed through four of the avr ? pins. in jtag terminology, these pins constitute the test access port ? tap. these pins are: tms: test mode select. this pin is used for na vigating through the tap-controller state machine. tck: test clock. jtag operation is synchronous to tck. tdi: test data in. serial input data to be shifted in to the instruction register or data register (scan chains). tdo: test data out. serial output data from instruction register or data register. the ieee std. 1149.1 also specifies an optional tap signal; trst ? test reset ? which is not provided. when the jtagen fuse is unprogrammed, these four tap pins are normal port pins, and the tap controller is in reset. when programmed, the input tap signals are internally pulled high and the jtag is enabled for boundary-scan and programming. the device is shipped with this fuse programmed. for the on-chip debug system, in addition to the jtag interface pins, the reset pin is monitored by the debugger to be able to detect external reset sources. the debugger can also pull the reset pin low to reset the wh ole system, assuming only open collectors on the reset line are used in the application. figure 24-1. block diagram ta p controller avr cpu boundary scan chain device boundary i/o port 0 tdi tdo tck tms i/o port n m u x instruction register id register bypass register jtag programming interface internal scan chain digital perpheral units jtag/ avr core communication interface analog peripheral units analog inputs control and clock lines breakpoint unit ocd status and control flow control unit flash memory address data pc instruction breakpoint scan chain address decoder 227 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 figure 24-2. tap controller state diagram 24.4 tap controller the tap controller is a 16-state finite st ate machine that controls the operatio n of the boundary-scan circuitry, jtag programming circuitry, or on-chip debug system. the state transitions depicted in figure 24-2 depend on the signal present on tms (shown adjacent to each state transition) at the time of the rising edge at tck. the initial state after a power-on reset is test-logic-reset. as a definition in this document, the lsb is shifted in and out first for all shift registers. assuming run-test/idle is the pres ent state, a typical scenario fo r using the jtag interface is: at the tms input, apply the sequence 1, 1, 0, 0 at the rising edges of tck to ente r the shift instruction register ? shift- ir state. while in this state, shift the four bits of the jtag instructions into the jtag instruction register from the tdi input at the rising edge of tck. the tms input must be held low during input of the 3lsbs in order to remain in the shift-ir state. the msb of the instructi on is shifted in when this state is left by setting tms high. while the instruction is shifted in from the tdi pin, the captured ir-state 0x01 is shifted out on the tdo pin. the jtag instruction selects a particular data register as path between tdi and tdo and controls the circuitry surrounding the selected data register. apply the tms sequence 1, 1, 0 to re-ent er the run-test/idle state. the instruct ion is latched onto the parallel output from the shift register path in the update-ir state. the exit-ir, pause-ir, and exit2- ir states are only used for navigating the state machine. test logic reset run test/idle select ir scan select dr scan capture ir capture dr 0 00 00 00 shift ir shift dr 11 exit1 ir exit1 dr exit2 ir exit2 dr 00 pause ir pause dr 11 update ir update dr 1 10 10 1 1 00 0 1 1 0 1 0 11 1 1 atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 228 at the tms input, apply the sequenc e 1, 0, 0 at the rising edges of tck to ent er the shift data register ? shift-dr state. while in this state, upload the selected data register (selected by the present jt ag instruction in th e jtag instruction register) from the tdi input at the rising edge of tck. in or der to remain in the shift-dr state, the tms input must be held low during input of all bits except th e msb. the msb of the data is shifted in when this state is left by setting tms high. while the data register is shifted in from the tdi pi n, the parallel inputs to the data register captured in the capture-dr state is shif ted out on the tdo pin. apply the tms sequence 1, 1, 0 to re- enter the run-test/idle st ate. if the selected data register has a latched parallel-output, the latching takes place in the update-dr state. t he exit-dr, pause-dr, and exit2-dr states are only used for navigating the state machine. as shown in the state diagram, the run- test/idle state need not be entered between selecting jtag instruction and using data registers, and some jtag instructions may select certain functions to be performed in the run-test/idle, making it unsuitable as an idle state. note: independent of the initial state of the tap controller, the test-logic-rese t state can always be entered by holding tms high for five tck clock periods. for detailed information on the jtag specific ation, refer to the literature listed in section 24.9 ?bibliography? on page 229 . 24.5 using the boundary-scan chain a complete description of the boundary- scan capabilities are given in the section section 25. ?ieee 1149.1 (jtag) boundary-scan? on page 231 . 24.6 using the on-chip debug system as shown in figure 24-1 on page 226 , the hardware support for on-chip debugging consists mainly of a scan chain on the interface between the internal avr ? cpu and the internal peripheral units. break point unit. communication interface betwe en the cpu and jtag system. all read or modify/write operations needed for implementing the debugger are done by applying avr instructions via the internal avr cpu scan chain. the cpu sends the result to an i/o memory mapped location which is part of the communication interface between the cpu and th e jtag system. the break point unit implements break on change of program flow, single step break, two program memory break points, and two combined break points. together, the four break points can be configured as either: 4 single program memory break points. 3 single program memory break point + 1 single data memory break point. 2 single program memory break points + 2 single data memory break points. 2 single program memory break points + 1 program me mory break point with mask (?range break point?). 2 single program memory break points + 1 data memory break point with mask (?range break point?). a debugger, like the avr studio ? , may however use one or more of these resources for its internal purpose, leaving less flexibility to the end-user. a list of the on-chip debug specific jtag instructions is given in section 24.7 ?on-chip debug specific jtag instructions? on page 229 . the jtagen fuse must be programmed to enable the jtag test access port. in addition, the ocden fuse must be programmed and no lock bits must be set for the on-chip de bug system to work. as a security feature, the on-chip debug system is disabled when either of the lb1 or lb2 lock bi ts are set. otherwise, the on-chip debug system would have provided a back-door into a secured device. the avr studio enables the user to fully control execution of programs on an avr device with on-chip debug capability, avr in-circuit emulator, or the built-in avr instruction set simulator. avr studio supports source level execution of assembly programs assembled with atmel corporation avr assembler and c programs compiled with third party vendors? compilers. avr studio runs under microsoft windows ? 95/98/2000 and microsoft windows nt ? . for a full description of the avr studio, please refer to the avr studio user guide. only highlights are presented in this document. 229 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 all necessary execution commands are available in avr studio ? , both on source level and on disassembly level. the user can execute the program, single step throu gh the code either by tracing into or step ping over functions, step out of functions, place the cursor on a statement and execut e until the statement is r eached, stop the execution, and reset the execution target. in additi on, the user can have an unlim ited number of code break points (using the break inst ruction) and up to two data memory break points, alternatively combined as a mask (range) break point. 24.7 on-chip debug specific jtag instructions the on-chip debug support is considered being privat e jtag instructions, and distributed within atmel ? and to selected third party vendors only. instruction opcodes are listed for reference. 24.7.1 private0; 0x8 private jtag instruction for accessing on-chip debug system. 24.7.2 private1; 0x9 private jtag instruction for accessing on-chip debug system. 24.7.3 private2; 0xa private jtag instruction for accessing on-chip debug system. 24.7.4 private3; 0xb private jtag instruction for accessing on-chip debug system. 24.8 using the jtag programming capabilities programming of avr ? parts via jtag is performed via the 4-pin jtag po rt, tck, tms, tdi, and tdo. these are the only pins that need to be controlled/observed to perform jtag programmi ng (in addition to power pins). it is not required to apply 12v externally. the jtagen fuse must be programmed and t he jtd bit in the mcucr register must be cleared to enable the jtag test access port. the jtag programming capability supports: flash programming and verifying. eeprom programming and verifying. fuse programming and verifying. lock bit programming and verifying. the lock bit security is exactly as in parallel programming m ode. if the lock bits lb1 or lb2 are programmed, the ocden fuse cannot be programmed unless first doing a chip erase. this is a security feature that ensures no back-door exists for reading out the content of a secured device. the details on programming through the jtag interface and programming specific jtag in structions are given in the section section 27.10 ?programming via t he jtag interface? on page 274 . 24.9 bibliography for more information about general boundary-scan, the following literature can be consulted: ieee: ieee std. 1149.1-1990. ieee st andard test access port and boundary-scan ar chitecture, ieee, 1993. colin maunder: the board designers guide to testable logic circuits, addison-wesley, 1992. atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 230 24.10 register description 24.10.1 ocdr ? on-chip debug register the ocdr register provides a communication channel from the running program in the microcontroller to the debugger. the cpu can transfer a byte to the debugger by writing to this loca tion. at the same time, an internal flag; i/o debug register dir ty ? idrd ? is set to indicate to the debugger that the register has been written. when the cpu reads the ocdr register the 7 lsb will be from the ocdr register, while the msb is the idrd bit. the debugger clears the idrd bit when it has read the information. in some avr ? devices, this register is shared with a standard i /o location. in this case, the ocdr register can only be accessed if the ocden fuse is programmed , and the debugger enables access to the ocdr register. in all other cases, the standard i/o location is accessed. refer to the debugger documentation for further information on how to use this register. bit 7 6543210 0x31 (0x51) msb/idrd lsb ocdr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 231 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 25. ieee 1149.1 (jtag) boundary-scan 25.1 features jtag (ieee std. 1149.1 compliant) interface boundary-scan capabilities according to the jtag standard full scan of all port functions as well as analog circuitry having off-chip connections supports the optional idcode instruction additional public avr_reset instruction to reset the avr 25.2 overview the boundary-scan chain has the capability of driving and observing the logic levels on the digital i/o pins, as well as the boundary between digital and analog logic for analog circuitry having off-chip connections. at system level, all ics having jtag capabilities are connected serially by the tdi/tdo signals to form a long shift register. an external controller sets up the devices to drive values at their output pins, and observe the input values received from other devices. the controller compares the received data with the ex pected result. in this way, boundary-sc an provides a mechanism for testing interconnections and integrity of comp onents on printed circuits boards by using the four tap signals only. the four ieee 1149.1 defined mandatory jtag instruct ions idcode, bypass, sample/preload, and extest, as well as the avr ? specific public jtag instruction avr_reset can be used for testing the pr inted circuit board. initial scanning of the data register path will show the id-code of the device, since idcode is the default jtag instruction. it may be desirable to have the avr device in reset during test mode. if not reset, inputs to the devic e may be determined by the scan operations, and the internal software may be in an undete rmined state when exiting the test mode. entering reset, the outputs of any port pin will inst antly enter the high impedance state, making the highz instruction redundant. if needed, the bypass instruction can be issued to make th e shortest possible scan chai n through the device. the device can be set in the reset state either by pulling the external reset pin low, or issuing the avr_reset inst ruction with approp riate setting of the reset data register. the extest instruction is used for sampling external pins and lo ading output pins with data. the data from the output latch will be driven out on the pins as soon as the extest instru ction is loaded into the jtag ir-register. therefore, the sample/preload should also be used for setting initial values to the scan ring, to avoid damaging the board when issuing the extest instruction for the first time . sample/preload can also be used for taking a snapshot of the external pins during normal operation of the part. the jtagen fuse must be programmed and the jtd bit in the i/o register mcucr must be cleared to enable the jtag test access port. when using the jtag interface for boundary-scan, using a jtag tck clock frequency higher than the internal chip frequency is possible. the chip clock is not required to run. 25.3 data registers the data registers relevant for boundary-scan operations are: bypass register device identification register reset register boundary-scan chain 25.3.1 bypass register the bypass register consists of a single shift register stage. when the bypass register is sele cted as path between tdi and tdo, the register is reset to 0 when leaving the capture-dr cont roller state. the bypass register can be used to shorten the scan chain on a system when the other devices are to be tested. atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 232 25.3.2 device identification register figure 25-1 shows the structure of the de vice identification register. figure 25-1. the format of the device identification register 25.3.2.1 version version is a 4-bit number identifying the revision of the comp onent. the jtag version number follows the revision of the device. revision a is 0x0, revision b is 0x1 and so on. 25.3.2.2 part number the part number is a 16-bit code identifying the component. t he jtag part number for atmel ? atmega164p-b/324p-b/644p-b is listed in table 27-6 on page 258 . 25.3.2.3 manufacturer id the manufacturer id is a 11-bit code identifying the manufact urer. the jtag manufacturer id for atmel is listed in table 27-6 on page 258 . 25.3.3 reset register the reset register is a test data register used to reset the part. since the avr tri-states por t pins when reset, the reset register can also replace the function of the unimplemented optional jtag instruction highz. a high value in the reset register corresponds to pulling the extern al reset low. the part is reset as long as there is a high value present in the reset register. depending on the fuse setti ngs for the clock options, the part will remain reset for a res et time-out period (refer to section 9.2 ?clock sources? on page 24 ) after releasing the reset register. the output from this data register is not latched, so the reset wil l take place immediately, as shown in figure 25-2 on page 232 . figure 25-2. reset register 25.3.4 boundary-scan chain the boundary-scan chain has the capability of driving and observing the logic levels on the digital i/o pins, as well as the boundary between digital and analog logic for analog circuitry having off-chip connections. see section 25.5 ?boundary-scan chain? on page 234 for a complete description. msb lsb bit 31 28 27 12 11 1 0 device id version part number manufacturer id 1 4 bits 16 bits 11 bits 1-bit q d internal reset from tdi clock dr avr_reset to tdo from other internal and external reset sources 233 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 25.4 boundary-scan specific jtag instructions the instruction register is 4-bit wide, supporting up to 16 inst ructions. listed below are the jt ag instructions useful for boundary-scan operation. note that the optio nal highz instruction is not implemented, but all output s with tri-state capability can be set in high-impedant state by using the avr_reset instru ction, since the initial state for all port pins is tri-state. as a definition in this datasheet, the lsb is shifted in and out first for all shift registers. the opcode for each instruction is show n behind the instruction name in hex format. the text describes which data register is selected as path betwe en tdi and tdo for each instruction. 25.4.1 extest; 0x0 mandatory jtag instruction for selecting the boundary-scan chain as data register fo r testing circuitry external to the avr ? package. for port-pins, pull-up disable, output control, output data, and input data are all accessible in the scan chain. for analog circuits having off-chip connections , the interface between the analog and the digital logic is in the scan chain. the contents of the latched out puts of the boundary-scan chain is driven out as soon as the jtag ir-register is loaded with the extest instruction. the active states are: capture-dr: data on the external pins are sampled into the boundary-scan chain. shift-dr: the internal scan chain is shifted by the tck input. update-dr: data from the scan chain is applied to output pins. 25.4.2 idcode; 0x1 optional jtag instruction selecting the 32 bit id-register as da ta register. the id-register co nsists of a version number, a device number and the manufacturer code chosen by jedec. this is the default instruction after power-up. the active states are: capture-dr: data in the idcode register is sampled into the boundary-scan chain. shift-dr: the idcode scan chain is shifted by the tck input. 25.4.3 sample_preload; 0x2 mandatory jtag instruction for pre-loading the output latc hes and taking a snap-shot of the input/output pins without affecting the system operation. however, the output latches are not connected to the pins. the boundary-scan chain is selected as data register. the active states are: capture-dr: data on the external pins are sampled into the boundary-scan chain. shift-dr: the boundary-scan chain is shifted by the tck input. update-dr: data from the boundary-scan chain is applied to the output latches. howeve r, the output latches are not connected to the pins. 25.4.4 avr_reset; 0xc the avr specific public jtag instruction for forcing the avr device into the reset mode or releasing the jtag reset source. the tap controller is not reset by this instruction. the one bit reset register is selected as dat a register. note that the res et will be active as long as there is a logic ?one? in the reset chain. the output from this chain is not latched. the active states are: shift-dr: the reset register is shifted by the tck input. 25.4.5 bypass; 0xf mandatory jtag instruction selecting th e bypass register for data register. the active states are: capture-dr: loads a logic ?0? into the bypass register. shift-dr: the bypass register cell between tdi and tdo is shifted. atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 234 25.5 boundary-scan chain the boundary-scan chain has the capability of driving and observing the logic levels on the digital i/o pins, as well as the boundary between digital and analog logic for analog circuitry having off-chip connection. 25.5.1 scanning the digital port pins figure 25-3 on page 235 shows the boundary-scan cell for a bi-directional por t pin. the pull-up function is disabled during boundary-scan when the jtag ic contains extest or sample_prel oad. the cell consists of a bi-directional pin cell that combines the three signals output control - ocxn, output data - odxn, and in put data - idxn, into only a two-stage shift register. the port and pin indexes are not used in the following description the boundary-scan logic is not included in the figures in the datasheet. figure 25-4 on page 236 shows a simple digital port pin as described in the section 14. ?i/o-ports? on page 57 . the boundary-scan details from figure 25-3 on page 235 replaces the dashed box in figure 25-4 on page 236 . when no alternate port function is present, the input data - id - corresponds to the pinxn register value (but id has no synchronizer), output data corresponds to t he port register, output control corresponds to the data direction - dd register, and the pull-up enable - puexn - corresponds to logic expression pud ddxn portxn. digital alternate port functions are connected outside the dotted box in figure 25-4 on page 236 to make the scan chain read the actual pin value. for analog function, there is a direct c onnection from the external pin to the analog circuit. there is n o scan chain on the interface between the digital and the analog circ uitry, but some digital control signal to analog circuitry a re turned off to avoid driving contention on the pads. when jtag ir contains extest or sample_ preload the clock is not sent out on th e port pins even if the ckout fuse is programmed. even though the clock is output when the jtag ir contains sam ple_preload, the cl ock is not sampled by the boundary scan. 235 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 figure 25-3. boundary-scan cell for bi-directional port pin with pull-up function ff1 from last cell clockdr updatedr port pin pxn) shiftdr pull-up enable (pue) output control (oc) output data (od) input data (id) to next cell extest v cc ld1 d 0 1 0 1 0 1 0 1 q d g q 0 1 0 1 ff0 ld0 dq d g q atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 236 figure 25-4. general port pin schematic diagram d q rrx pxn clr reset synchronizer see boundary scan description for details! data bus portxn q q l d clr q q d q reset rpx pull-up disable pull-up enable for pin pxn wdx: write ddrx pud: sleep control sleep: input data from pin pxn idxn: output control for pin pxn output data to pin pxn ocxn: odxn: wrx: clk: i/o rpx: rrx: read portx register read portx pin i/o clock rdx: write portx read ddrx puexn: rdx clk i/o pud puexn ocxn sleep odxn idxn wdx d q clr ddxn q wrx 237 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 25.5.2 scanning the reset pin the reset pin accepts 5v active low logic for standard reset operation, and 12v active high logic for high voltage parallel programming. an observe-only cell as shown in figure 25-5 is inserted for the 5v reset signal. figure 25-5. observe-only cell 25.6 atmega164p-b/324p-b/644p-b boundary-scan order table 25-1 shows the scan order between tdi and tdo when the boundar y-scan chain is selected as data path. bit 0 is the lsb; the first bit scanned in, and the first bit scanned out. t he scan order follows the pin-out order as far as possible. therefore, the bits of port a and port k is scanned in the opposite bit order of the other ports. exceptions from the rules are the scan chains for the analog circuits, which constitute the most significant bits of the scan chain regardless of which physical pin they are connected to. in figure 25-3 on page 235 , pxn. data corresponds to ff0, pxn. control corresponds to ff1, pxn. bit 4, 5, 6 and 7 of port f is not in the scan chain, since these pins constitute the tap pins when the jtag is enabled. ff1 shiftdr from system pin to system logic to next cell from previous cell clockdr d 0 1 q table 25-1. atmega164p-b/324p-b/644p-b boundary-scan order bit number signal name module 56 pb0.data port b 55 pb0.control 54 pb1.data 53 pb1.control 52 pb2.data 51 pb2.control 50 pb3.data 49 pb3.control 48 pb4.data 47 pb4.control 46 pb5.data 45 pb5.control 44 pb6.data 43 pb6.control 42 pb7.data 41 pb7.control atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 238 40 rstt reset logic (observe only) 39 pd0.data port d 38 pd0.control 37 pd1.data 36 pd1.control 35 pd2.data 34 pd2.control 33 pd3.data 32 pd3.control 31 pd4.data 30 pd4.control 29 pd5.data 28 pd5.control 27 pd6.data 26 pd6.control 25 pd7.data 24 pd7.control 23 pc0.data port c 22 pc0.control 21 pc1.data 20 pc1.control 19 pc6.data 18 pc6.control 17 pc7.data 16 pc7.control 15 pa7.data 14 pa7.control port a 13 pa6.data 12 pa6.control 11 pa5.data 10 pa5.control 9 pa4.data 8 pa4.control 7 pa3.data 6 pa3.control 5 pa2.data 4 pa2.control 3 pa1.data 2 pa1.control 1 pa0.data 0 pa0.control table 25-1. atmega164p-b/324p-b/644p-b boundary-scan order (continued) bit number signal name module 239 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 25.7 boundary-scan description language files boundary-scan description language (bsdl) files describe bo undary-scan capable devices in a standard format used by automated test-generation software. the orde r and function of bits in the boundary- scan data register are included in this description. bsdl files are available for atmel ? atmega164p-b/324p-b/644p-b. 25.8 register description 25.8.1 mcucr ? mcu control register the mcu control register contains c ontrol bits for general mcu functions. ? bits 7 ? jtd: jtag interface disable when this bit is zero, the jtag interface is enabled if the jtag en fuse is programmed. if this bit is one, the jtag interface is disabled. in order to avoid unintentional disabling or enabl ing of the jtag interface, a timed sequence must be followed when changing this bit: the application software must write this bit to the de sired value twice within fo ur cycles to change it s value. note that this bit must not be altered when using the on-chip debug system. 25.8.2 mcusr ? mcu status register the mcu status register provides informati on on which reset source caused an mcu reset. ? bit 4 ? jtrf: jtag reset flag this bit is set if a reset is being caused by a logic one in the jtag reset register sele cted by the jtag instruction avr_reset. this bit is reset by a power-on reset, or by writ ing a logic zero to the flag. bit 76 5 43210 0x35 (0x55) jtd bods bodse pud ? ? ivsel ivce mcucr read/write r/w r/w r/w r/w r r r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 0x34 (0x54) ? ? ?jtrf wdrf borf extrf porf mcusr read/write r r r r/w r/w r/w r/w r/w initial value 0 0 0 see bit description atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 240 26. boot loader support ? read-w hile-write self-programming 26.1 features read-while-write self-programming flexible boot memory size high security (separate boot lock bits for a flexible protection) separate fuse to select reset vector optimized page (1) size code efficient algorithm efficient read-modify-write support note: 1. a page is a section in the flash consisting of several bytes (see table 27-7 on page 258 ) used during programming. the page organization does not affect normal operation. 26.2 overview the boot loader support provides a real read-while-write self-programming mechanism for downloading and uploading program code by the mcu itself. this feature allows flexible application software updates controlled by the mcu using a flash-resident boot loader program. the b oot loader program can use any available data interface and associated protocol to read code and write (program) that code into the flash memory , or read the code from the program memory. the program code within the boot loader section has the capability to write into the entire flash, including the boot loader memory. the boot loader can thus even modify itself, and it can also erase it self from the code if the feat ure is not needed anymore. the size of the boot loader memory is configurable with fuses and the boot loader has two separate sets of boot lock bits which can be set independently. this gives the user a unique fl exibility to select different levels of protection. 26.3 application and boot loader flash sections the flash memory is organized in two main sections , the application section and the boot loader section (see figure 26-2 on page 242 ). the size of the different sections is co nfigured by the bootsz fuses as shown in table 26-10 on page 251 and figure 26-2 on page 242 . these two sections can have differen t level of protection since they have different sets of lock bits. 26.3.1 application section the application section is the section of the flash that is used for storing the app lication code. the protection level for the application section can be selected by the app lication boot lock bits (boot lock bits 0), see table 26-2 on page 243 . the application section can never st ore any boot loader code since the spm instru ction is disabled when executed from the application section. 26.3.2 bls ? boot loader section while the application section is used for st oring the application code, the the boot loader software must be located in the bls since the spm instruction can initiate a programming w hen executing from the bls only. the spm instruction can access the entire flash, including the bls itself. the protection level fo r the boot loader section ca n be selected by the boot loader lock bits (boot lock bits 1), see table 26-3 on page 243 . 241 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 26.4 read-while-write and no read-while-write flash sections whether the cpu supports read-while-write or if the cpu is halted during a boot loader so ftware update is dependent on which address that is being programmed. in addition to the two sections that are configurable by the bootsz fuses as described above, the flash is also divided into two fixed sections, the read-while-write (rww) section and the no read-while-write (nrww) section. the limit between the rww- and nrww sections is given in table 26-1 and figure 26-1 on page 242 . the main difference between the two sections is: when erasing or writing a page located inside the rw w section, the nrww section can be read during the operation. when erasing or writing a page located inside the nrww section, the cpu is halted during the entire operation. note that the user software can never re ad any code that is locat ed inside the rww section durin g a boot loader software operation. the syntax ?read-while-write section? refers to whic h section that is being progra mmed (erased or written), not which section that actually is being re ad during a boot loader software update. 26.4.1 rww ? read-wh ile-write section if a boot loader software update is programming a page inside th e rww section, it is possible to read code from the flash, but only code that is located in the nrww section. during an on-going programming, the software must ensure that the rww section never is being read. if the user software is trying to read code that is located inside the rww section (i.e., by load program memory, call, or jump inst ructions or an interrupt) during progra mming, the software might end up in an unknown state. to avoid this, the interrupts should either be disabled or moved to the boot loader section. the boot loader section is always located in the nrww section. the rww sect ion busy bit (rwwsb) in the store program memory control and status register (spmcsr) will be read as logical one as long as the rww section is blocked for reading. after a programming is completed, the rwwsb must be cleared by soft ware before reading code located in the rww section. see section 26.9.1 ?spmcsr ? store program memory control and status register? on page 253 for details on how to clear rwwsb. 26.4.2 nrww ? no read-while-write section the code located in the nrww section can be read when the boo t loader software is updating a page in the rww section. when the boot loader code updates the nrww section, the cpu is halted during the entire page erase or page write operation. table 26-1. read-while-write features which section does the z-pointer address during the programming? which section can be read during programming? is the cpu halted? read-while-write supported? rww section nrww section no yes nrww section none yes no atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 242 figure 26-1. read-while-write versus no read-while-write figure 26-2. memory sections note: the parameters in the figure above are given in table 26-10 on page 251 . z-pointer addresses rww section code located in nrww section can be read during the operation z-pointer addresses nrww section cpu is halted during the operation read while write (rww) section no read while write (rww) section program memory bootsz = 11 0x0000 flashend read-while write section no read-while write section end rww start nrww end application start boot loader program memory bootsz = 10 0x0000 flashend read-while write section no read-while write section end rww start nrww end application start boot loader program memory bootsz = 01 0x0000 flashend read-while write section no read-while write section end rww start nrww end application start boot loader program memory bootsz = 00 0x0000 flashend read-while write section no read-while write section end rww, end application start nrww, start boot loade r application flash section application flash section boot loader flash section boot loader flash section application flash section application flash section boot loader flash section application flash section application flash section boot loader flash section application flash section 243 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 26.5 boot loader lock bits if no boot loader capability is needed, the entire flash is available for application code. the boot loader has two separate se ts of boot lock bits which can be set independently. this gives the us er a unique flexibility to select different levels of protec tion. the user can select: to protect the entire flash from a software update by the mcu. to protect only the boot loader flash se ction from a software update by the mcu. to protect only the application flash se ction from a software update by the mcu. allow software update in the entire flash. see table 26-2 and table 26-3 for further details. the boot lock bits can be set in software and in serial or parallel programming mode, but they can be cleared by a chip eras e command only. the general write lock (lock bit mode 2) does not allow the programming of the flash memo ry by spm instruction. si milarly, the general read/write lock (lock bit mode 3) does not allow reading nor writing by (e)lpm/spm, if it is attempted. table 26-2. boot lock bit0 protecti on modes (application section) (1) blb0 mode blb02 blb01 protection 1 1 1 no restrictions for spm or (e)lpm accessing the application section. 2 1 0 spm is not allowed to write to the application section. 3 0 0 spm is not allowed to write to the app lication section, and (e)lpm executing from the boot loader section is not allowed to read from the application section. if interrupt vectors are placed in the boot loader section, interrupts are disabled while executing from the application section. 4 0 1 (e)lpm executing from the boot loader section is not allowed to read from the application section. if interrupt ve ctors are placed in the boot loader section, interrupts are disabled while executing from the application section. note: 1. ?1? means unprogrammed, ?0? means programmed table 26-3. boot lock bit1 protecti on modes (boot loader section) (1) blb1 mode blb12 blb11 protection 1 1 1 no restrictions for spm or (e)l pm accessing the boot loader section. 2 1 0 spm is not allowed to write to the boot loader section. 3 0 0 spm is not allowed to write to the boot loader section, and (e)lpm executing from the application section is not allowed to read from the boot loader section. if interrupt vectors are placed in the application section, interrupts are disabled while executing from the boot loader section. 4 0 1 (e)lpm executing from the application se ction is not allowed to read from the boot loader section. if interrupt vectors are placed in the application section, interrupts are disabled while executing from the boot loader section. note: 1. ?1? means unprogrammed, ?0? means programmed atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 244 26.6 entering the boot loader program entering the boot loader takes place by a jump or call from the application program. this may be initiated by a trigger such as a command received via usart, or spi interface. alternativ ely, the boot reset fuse can be programmed so that the reset vector is pointing to the boot flash start address after a reset. in this case, the boot loader is started after a reset. after the application code is loaded, the program c an start executing the application code. no te that the fuses cannot be changed by the mcu itself. this means that once the b oot reset fuse is programmed, the reset ve ctor will always point to the boot loader reset and the fuse can only be changed through the serial or parallel programming interface. 26.7 addressing the flash during self-programming the z-pointer is used to address the spm commands. the z pointer c onsists of the z-registers zl and zh in the register file, and rampz in the i/o space. the number of bits actually used is implementation dependent. note that the rampz register is only implemented when the program space is larger than 64kbytes. since the flash is organized in pages (see table 27-7 on page 258 ), the program counter can be treated as having two different sections. one section, consisting of the least significant bits, is addre ssing the words within a page, while the mos t significant bits are addressing the pages. this is shown in figure 26-3 on page 245 . note that the page erase and page write operations are addressed independently. ther efore it is of major importance that the boot loader software addresses the same page in both the page erase and page write operation. once a programming operation is initiated, the address is latched and the z-pointer can be used for other operations. the lpm instruction use the z-pointer to store the address. si nce this instruction addresses the flash byte-by-byte, also bit z0 of the z-pointer is used. table 26-4. boot reset fuse (1) bootrst reset address 1 reset vector = application reset (address 0x0000) 0 reset vector = boot loader reset (see table 26-10 on page 251 ) note: 1. ?1? means unprogrammed, ?0? means programmed bit 2322212019181716 15 14 13 12 11 10 9 8 rampz rampz7 rampz6 rampz5 rampz4 rampz3 rampz2 rampz1 rampz0 zh (r31) z15 z14 z13 z12 z11 z10 z9 z8 zl (r30) z7 z6 z5 z4 z3 z2 z1 z0 76543210 245 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 figure 26-3. addressing the flash during spm (1) note: 1. the different variables used in figure 26-3 are listed in table 26-12 on page 252 . 26.8 self-programming the flash the program memory is updated in a page by page fashion. before programming a page with the data stored in the temporary page buffer, the page must be erased. the temporary page buffer is filled one word at a time using spm and the buffer can be filled either before the page erase command or between a pag e erase and a page write operation: alternative 1, fill the buffer before a page erase fill temporary page buffer perform a page erase perform a page write alternative 2, fill the buffer after page erase perform a page erase fill temporary page buffer perform a page write if only a part of the page needs to be changed, the rest of the page must be st ored (for example in the temporary page buffer) before the erase, and then be rewritten. when usin g alternative 1, the boot load er provides an effective read-modify-write feature which allows the user software to first read the page, do the necessary changes, and then write back the modified data. if alternative 2 is used, it is not po ssible to read the old data while loading since the page is alrea dy erased. the temporary page buffer can be accessed in a random sequence. it is e ssential that the page address used in both the page erase and page write opera tion is addressing the same page. see section 26.8.13 ?simple assembly code example for a boot loader? on page 249 for an assembly code example. bit pagemsb pcmsb zpagemsb zpcmsb 0 1 15 z-register program counter word address within page page address within the flash 0 pcword pcpage 02 01 00 pageend pcword [pagemsb : 0] page program memory instructions word page atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 246 26.8.1 performing page erase by spm to execute page erase, set up the address in the z-pointer , write ?x0000011? to spmcsr and execute spm within four clock cycles after writing spmcsr. the data in r1 and r0 is ignored. the page address must be written to pcpage in the z-register. other bits in the z-pointe r will be ignored during this operation. page erase to the rww section: the nrww section can be read during the page erase. page erase to the nrww section: the cpu is halted during the operation. note: if an interrupt occurs in the ti me sequence, the f our cycle access cannot be guarant eed. in order to ensure atomic operation, you should disable interrupts before writing to spmcsr. 26.8.2 filling the temporar y buffer (page loading) to write an instruction word, set up the address in the z- pointer and data in r1:r0, write ?00000001? to spmcsr and execute spm within four clock cycles after writing spmcsr. t he content of pcword in the z-register is used to address the data in the temporary buffer. the te mporary buffer will auto-erase after a pag e write operation or by writing the rwwsre bit in spmcsr. it is also erased after a system reset. no te that it is not possible to write more than one time to each address without erasing the temporary buffer. if the eeprom is written in the middle of an spm page load operation, all data loaded will be lost. 26.8.3 performing a page write to execute page write, set up the address in the z-pointer, write ?x0000101? to spmcsr and execute spm within four clock cycles after writing spmcsr. the data in r1 and r0 is ignore d. the page address must be written to pcpage. other bits in the z-pointer must be written to zero during this operation. page write to the rww section: the nrww section can be read during the page write. page write to the nrww section: t he cpu is halted during the operation. 26.8.4 using the spm interrupt if the spm interrupt is enabled, the spm interrupt will gener ate a constant inte rrupt when the spmen bit in spmcsr is cleared. this means that the interrupt can be used instead of polling the spmcsr register in software. when using the spm interrupt, the interrupt vectors should be moved to the bls sect ion to avoid that an interrupt is accessing the rww section when it is blocked for reading. how to move the interrupts is described in section 12. ?interrupts? on page 49 . 26.8.5 consideration while updating bls special care must be taken if the user allows the boot loader section to be updated by leaving boot lock bit11 unprogrammed. an accidental write to the boot loader itself can corrupt the entire boot loader, and further software updates might be impossible. if it is not necessary to change the boot loader software itse lf, it is recommended to program the boot lock bit11 to protect the boot loader softw are from any internal software changes. 26.8.6 prevent reading the rww section during self-programming during self-programming (either page erase or page write) , the rww section is always blocked for reading. the user software itself must prevent that this section is addressed during the self programming operation. the rwwsb in the spmcsr will be set as long as the rww section is busy. duri ng self-programming the interrupt vector table should be moved to the bls as described in section 12. ?interrupts? on page 49 , or the interrupts must be disabled. before addressing the rww section after the programming is completed, the us er software must clear the rwwsb by writing the rwwsre. see section 26.8.13 ?simple assembly code example for a boot loader? on page 249 for an example. 247 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 26.8.7 setting the boot loader lock bits by spm to set the boot loader lock bits and general lock bits, write the desired data to r0, write ?x0001001? to spmcsr and execute spm within four clock cycles after writing spmcsr. see table 26-2 on page 243 and table 26-3 on page 243 for how the different settings of the boot loader bits affect the flash access. if bits 5..0 in r0 are cleared (zero), the corresponding boot lock bit will be programmed if an spm instruction is executed within four cycles after blbset and spmen are set in spmcsr. the z-pointer is don?t care during this operation, but for future compatibility it is recommended to load the z-pointer with 0x0001 (same as used for reading the lo ck bits). for future compatibility it is also recommended to set bits 7 and 6 in r0 to ?1? when writing the lock bits. when programming the lock bits the entire flash can be read during the operation. 26.8.8 eeprom write prevents writing to spmcsr note that an eeprom write operation will block all software programming to flash. reading the fuses and lock bits from software will also be prevented during the eeprom write operati on. it is recommended that t he user checks the status bit (eepe) in the eecr register and veri fies that the bit is cleared befo re writing to the spmcsr register. 26.8.9 reading the fuse and lock bits from software it is possible to read both the fuse and lock bits from soft ware. to read the lock bits, load the z-pointer with 0x0001 and set the blbset and spmen bits in spmcsr. when an (e)lpm in struction is executed within three cpu cycles after the blbset and spmen bits are set in spmcsr, the value of the lock bits will be loaded in the destination register. the blbset and spmen bits will auto-clear upon completion of read ing the lock bits or if no (e )lpm instruction is executed within three cpu cycles or no spm instruction is executed within four cpu cycles. when blbset and spmen are cleared, (e)lpm will work as described in the instruction set manual. the algorithm for reading the fuse low byte is similar to the one described above for reading the lock bits. to read the fuse low byte, load the z-pointer with 0x0000 and set the blbset and spmen bits in spmcsr. when an (e)lpm instruction is executed within three cycles afte r the blbset and spmen bits are set in the spmcsr, the value of the fuse low byte (flb) will be loaded in the destination register as shown below. refer to table 27-5 on page 257 for a detailed description and mapping of the fuse low byte. similarly, when reading the fuse high byte, load 0x0003 in the z-pointer. when an (e)lpm instruction is executed within three cycles after the blbset and spmen bits are set in the sp mcsr, the value of the fuse high byte (fhb) will be loaded in the destination register as shown below. refer to table 27-4 on page 257 for detailed description and mapping of the fuse high byte. when reading the extended fuse byte, load 0x0002 in the z-poin ter. when an (e)lpm instructi on is executed within three cycles after the blbset and spmen bits are set in the spmcsr , the value of the extended fuse byte (efb) will be loaded in the destination register as shown below. refer to table 27-3 on page 256 for detailed description and mapping of the extended fuse byte. fuse and lock bits that are programmed, will be read as zero . fuse and lock bits that are unprogrammed, will be read as one. bit 76543210 r0 1 1 blb12 blb11 blb02 blb01 lb2 lb1 bit 76543210 rd ? ? blb12 blb11 blb02 blb01 lb2 lb1 bit 76543210 rd flb7 flb6 flb5 flb4 flb3 flb2 flb1 flb0 bit 76543210 rd fhb7 fhb6 fhb5 fhb4 fhb3 fhb2 fhb1 fhb0 bit 76543210 rd ? ? ? ? ? efb2 efb1 efb0 atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 248 26.8.10 reading the signature row from software to read the signature row from software, load the z-pointer with the signature byte address given in table 26-5 and set the sigrd and spmen bits in spmcsr. when an lpm instruction is ex ecuted within three cpu cycl es after the sigrd and spmen bits are set in spmcsr, the signature byte value will be loaded in the destination register. the sigrd and spmen bits will auto-clear upon completion of reading the signature ro w lock bits or if no lpm instruction is executed within three cpu cycles. when sigrd and spmen are cleared, lpm will work as described in the instruction set manual. 26.8.11 preventing flash corruption during periods of low v cc , the flash program can be corrupted because th e supply voltage is too low for the cpu and the flash to operate properly. these issues are the same as for board level systems using the flash, and the same design solutions should be applied. a flash program corruption can be caused by two situations wh en the voltage is too low. firs t, a regular write sequence to the flash requires a minimum voltage to operate correctly. second ly, the cpu itself can execute instructions incorrectly, if th e supply voltage for executing instructions is too low. flash corruption can easily be avoided by followin g these design recommendations (one is sufficient): 1. if there is no need for a boot loader update in the system, program the boot loader lock bits to prevent any boot loader software updates. 2. keep the avr ? reset active (low) during peri ods of insufficient power supply voltage. this can be done by enabling the internal brown-out detector (bod) if the o perating voltage matches the detection level. if not, an external low v cc reset protection circuit can be used. if a reset occurs while a write operation is in progress, the write operation will be completed provided that the power supply voltage is sufficient. 3. keep the avr core in power-down sleep mode during periods of low v cc . this will prevent the cpu from attempting to decode and execut e instructions, effectively pr otecting the spmcsr register and thus the flash from unintentional writes. 26.8.12 programming time for flash when using spm the calibrated rc oscillator is used to time flash accesses. table 26-6 shows the typical prog ramming time for flash accesses from the cpu. table 26-5. signature row addressing signature byte z-pointer address device signature byte 1 0x0000 device signature byte 2 0x0002 device signature byte 3 0x0004 rc oscillator calibration byte 3v 0x0001 rc oscillator calibration byte 5v 0x0003 note: all other addresses are reserved for future use. table 26-6. spm programming time (1) symbol min programming time max programming time flash write (page erase, p age write, and write lock bits by spm) 3.7ms 4.5ms note: 1. minimum and maximum programming times is per individual operation. 249 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 26.8.13 simple assembly code example for a boot loader ;-the routine writes one page of data from ram to flash ; the first data location in ram is pointed to by the y pointer ; the first data location in flash is pointed to by the z-pointer ;-error handling is not included ;-the routine must be placed inside the boot space ; (at least the do_spm sub routine). only code inside nrww section can ; be read during self-programming (page erase and page write). ;-registers used: r0, r1, temp1 (r16), temp2 (r17), looplo (r24), ; loophi (r25), spmcrval (r20) ; storing and restoring of registers is not included in the routine ; register usage can be optimized at the expense of code size ;-it is assumed that either the interrupt table is moved to the boot ; loader section or that the interrupts are disabled. .equ pagesizeb = pagesize*2;pagesizeb is page size in bytes, not words .org smallbootstart write_page: ;page erase ldi spmcrval, (1< atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 252 26.8.16 zatmega644p-b boot loader parameters in table 26-13 through table 26-15 on page 253 , the parameters used in the description of the self-programming are given. table 26-12. explanation of di fferent variables used in figure 26-3 on page 245 and the mapping to the z-pointer variable corresponding z-value description (1) pcmsb 13 most significant bit in the program c ounter. (the program counter is 14 bits pc[13:0]) pagemsb 6 most significant bit which is used to address the words within one page (128 words in a page requires seven bits pc [5:0]). zpcmsb z14 bit in z-pointer that is mapped to pcmsb. because z0 is not used, the zpcmsb equals pcmsb + 1. zpagemsb z7 bit in z-pointer that is mapped to pcmsb. because z0 is not used, the zpagemsb equals pagemsb + 1. pcpage pc[13:6] z14:z7 program counter page address: page select, for page erase and page write pcword pc[5:0] z6:z1 program counter word address: word select, for filling temporary buffer (must be zero during page write operation) note: 1. 0: should be zero for all spm commands, byte select for the (e)lpm instruction. see section 26.7 ?addressing the flash during self-programming? on page 244 for details about the use of z-pointer during self-programming. table 26-13. boot size configuration (1) bootsz1 bootsz0 boot size pages application flash section boot loader flash section end application section boot reset address (start boot loader section) 1 1 512 words 4 0x0000 - 0x7dff 0x7e00 - 0x7fff 0x7dff 0x7e00 1 0 1024 words 8 0x0000 - 0x7bff 0x7c00 - 0x7fff 0x7bff 0x7c00 0 1 2048 words 16 0x0000 - 0x77ff 0x7800 - 0x7fff 0x77ff 0x7800 0 0 4096 words 32 0x0000 - 0x6fff 0x7000 - 0x7fff 0x6fff 0x7000 note: 1. the different bootsz fuse configurations are shown in figure 26-2 on page 242 . table 26-14. read-whi le-write limit (1) section pages address read-while-write section (rww) 224 0x0000 - 0x6fff no read-while-write section (nrww) 32 0x7000 - 0x7fff note: 1. for details about these two sections, see section 26.4.2 ?nrww ? no read-while-write section? on page 241 and section 26.4.1 ?rww ? read-while-write section? on page 241 . 253 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 see section 26.7 ?addressing the flash during self-programming? on page 244 for details about the use of z-pointer during self-programming. 26.9 register description 26.9.1 spmcsr ? store program memory control and status register the store program memory control and status register contains the control bits n eeded to control the boot loader operations. ? bit 7 ? spmie: spm interrupt enable when the spmie bit is written to one, and the i-bit in the stat us register is set (one), the spm ready interrupt will be enable d. the spm ready interrupt will be executed as long as the spmen bit in the spmcsr register is cleared. ? bit 6 ? rwwsb: read-while-write section busy when a self-programming (page erase or page write) operati on to the rww section is initiated, the rwwsb will be set (one) by hardware. when the rwwsb bit is set, the rww sect ion cannot be accessed. the rwwsb bit will be cleared if the rwwsre bit is written to one afte r a self-programming operation is completed. alternatively the rwwsb bit will automatically be cleared if a pa ge load operation is initiated. ? bit 5 ? sigrd: signature row read if this bit is written to one at the same time as spmen, the next lpm instruction within thr ee clock cycles will read a byte fr om the signature row into the destination register. see section 26.8.10 ?reading the signature row from software? on page 248 for details. an spm instructi on within four cycles after sigr d and spmen are set will have no effect. this operation is reserved for future use and should not be used. ? bit 4 ? rwwsre: read-while-write section read enable when programming (page erase or page write) to the rww section, the rww section is blocked for reading (the rwwsb will be set by hardware). to re-enable t he rww section, the user software must wait until the programming is completed (spmen will be cleared). then, if the rwwsre bit is written to one at the same time as spmen, the next spm instruction within four clock cycles re-enables the rww section. the rww section cannot be re-enabled while the flash is busy with a page erase or a page write (spmen is set). if the rwwsre bit is written while the flash is being loaded, the flash load operation will abort and the data loaded will be lost. table 26-15. explanation of di fferent variables used in figure 26-3 on page 245 and the mapping to the z-pointer variable corresponding z-value description (1) pcmsb 14 most significant bit in the program counter. (the program counter is 14 bits pc[14:0]) pagemsb 7 most significant bit which is used to address the words within one page (128 words in a page requires seven bits pc [6:0]). zpcmsb z15 bit in z-pointer that is mapped to pcmsb. because z0 is not used, the zpcmsb equals pcmsb + 1. zpagemsb z8 bit in z-pointer that is mapped to pcmsb. because z0 is not used, the zpagemsb equals pagemsb + 1. pcpage pc[14:7] z15:z7 program counter page address: page select, for page erase and page write pcword pc[6:0] z7:z1 program counter word address: word select, for filling temporary buffer (must be zero during page write operation) note: 1. z0: should be zero for all spm comma nds, byte select for th e (e)lpm instruction. bit 765 4 3 210 0x37 (0x57) spmie rwwsb sigrd rwwsre blbset pgwrt pgers spmen spmcsr read/write r/w r r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 254 ? bit 3 ? blbset: boot lock bit set if this bit is written to one at the same time as spmen, the next spm instructi on within four clock cycles sets boot lock bits, according to the data in r0. the data in r1 and the address in the z-pointer are ignored. the blbset bit will automatically be cleared upon completion of the lock bit set, or if no spm instruction is executed within four clock cycles. an (e)lpm instruction within three cycles after blbset and spmen are set in the spmcsr register, will read either the lock bits or the fuse bits (depending on z0 in the z-pointer) into the destination register. see section 26.8.9 ?reading the fuse and lock bits from software? on page 247 for details. ? bit 2 ? pgwrt: page write if this bit is written to one at the sa me time as spmen, the next spm instruction within four clock cycles executes page write, with the data stored in the temporary buffer. the page address is taken from the high part of the z-pointer. the data in r1 and r0 are ignored. the pgwrt bit will auto-clear upon completi on of a page write, or if no spm instruction is executed within four clock cycles. the cpu is halte d during the entire page write operation if the nrww section is addressed. ? bit 1 ? pgers: page erase if this bit is written to one at the same time as spme n, the next spm instru ction within four clo ck cycles executes page erase. the page address is taken from the high part of the z-pointer. the data in r1 and r0 are ignored. the pgers bit will auto-clear upon completion of a page erase, or if no spm instru ction is executed within four cl ock cycles. the cpu is halted during the entire page writ e operation if the nrww section is addressed. ? bit 0 ? spmen: store program memory enable this bit enables the spm instruction for the next four clock cy cles. if written to one together with either rwwsre, blbset, pgwrt? or pgers, the following spm instruction will have a special meaning, see description above. if only spmen is written, the following spm instruction will store the value in r1:r0 in the temporar y page buffer addressed by the z-pointer. the lsb of the z-pointer is ignored. the spmen bit will auto- clear upon completion of an spm instruction, or if no spm instruction is executed within four clock cycles. during pag e erase and page write, the spm en bit remains high until the operation is completed. writing any other combination than ?10001?, ?01001?, ?00101?, ?00011 ? or ?00001? in the lower five bits will have no effect. note: only one spm instruction sh ould be active at any time. 255 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 27. memory programming 27.1 program and data memory lock bits the atmel ? atmega164p-b/324p-b/644p-b provides six lock bits which can be left unprogrammed (?1?) or can be programmed (?0?) to obtain the additional features listed in table 27-2 . the lock bits can only be erased to ?1? with the chip erase command. table 27-1. lock bit byte (1) lock bit byte bit no description default value 7 ? 1 (unprogrammed) 6 ? 1 (unprogrammed) blb12 5 boot lock bit 1 (unprogrammed) blb11 4 boot lock bit 1 (unprogrammed) blb02 3 boot lock bit 1 (unprogrammed) blb01 2 boot lock bit 1 (unprogrammed) lb2 1 lock bit 1 (unprogrammed) lb1 0 lock bit 1 (unprogrammed) note: 1. ?1? means unprogrammed, ?0? means programmed. table 27-2. lock bit protection modes (1)(2) memory lock bits protection type lb mode lb2 lb1 1 1 1 no memory lock features enabled. 2 1 0 further programming of th e flash and eeprom is di sabled in parallel and serial programming mode. the fuse bits are locked in both serial and parallel programming mode. (1) 3 0 0 further programming and verification of the flash and eeprom is disabled in parallel, jtag and serial programming mode. the boot lock bits and fuse bits are locked in both serial and parallel programming mode. (1) blb0 mode blb02 blb01 1 1 1 no restrictions for spm or (e)lpm accessing the application section. 2 1 0 spm is not allowed to writ e to the application section. 3 0 0 spm is not allowed to write to the app lication section, and (e)lpm executing from the boot loader section is not allowed to read from the application section. if interrupt vectors are placed in the boot loader section, interrupts are disabled while executing from the application section. 4 0 1 (e)lpm executing from the boot loader section is not allowed to read from the application section. if interrupt vectors are placed in the boot loader section, interrupts are disabled while executing from the application section. notes: 1. program the fuse bits and boot lock bits before programming the lb1 and lb2. 2. ?1? means unprogrammed, ?0? means programmed atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 256 27.2 fuse bits the atmel ? atmega164p-b/324p-b/644p-b has four fuse bytes. table 27-3 - table 27-5 on page 257 describe briefly the functionality of all the fuses and how they are mapped into the fuse bytes. note that the fuses are read as logical zero, ?0?, if they are programmed. blb1 mode blb12 blb11 1 1 1 no restrictions for spm or (e)lpm accessing the boot loader section. 2 1 0 spm is not allowed to write to the boot loader section. 3 0 0 spm is not allowed to write to the boot loader section, and (e)lpm executing from the application section is not a llowed to read from the boot loader section. if interrupt vectors are placed in the application section, interrupts are disabled while executing from the boot loader section. 4 0 1 (e)lpm executing from the application se ction is not allowed to read from the boot loader section. if interrupt vector s are placed in the application section, interrupts are disabled while executing from the boot loader section. table 27-2. lock bit protection modes (1)(2) (continued) memory lock bits protection type notes: 1. program the fuse bits and boot lock bits before programming the lb1 and lb2. 2. ?1? means unprogrammed, ?0? means programmed table 27-3. extended fuse byte fuse low byte bit no description default value ? 7 ? 1 ? 6 ? 1 ? 5 ? 1 ? 4 ? 1 ? 3 ? 1 bodlevel2 (1) 2 brown-out detector trigger level 1 (unprogrammed) bodlevel1 (1) 1 brown-out detector trigger level 0 (programmed) bodlevel0 (1) 0 brown-out detector trigger level 1 (unprogrammed) note: 1. see section 28.5 ?system and reset characteristics? on page 291 for bodlevel fuse decoding (default = 2.7v). 257 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 the status of the fuse bits is not affected by chip erase. note that the fuse bits are locked if lock bit1 (lb1) is programmed. program the fuse bits before programming the lock bits. 27.2.1 latching of fuses the fuse values are latched when the device enters programming mode and changes of the fuse values will have no effect until the part leaves programming mode. this does not ap ply to the eesave fuse which will take effect once it is programmed. the fuses are also latched on power-up in normal mode. table 27-4. fuse high byte fuse high byte bit no description default value ocden (4) 7 enable ocd 1 (unprogrammed, ocd disabled) jtagen 6 enable jtag 0 (programmed, jtag enabled) spien (1) 5 enable serial program and data downloading 0 (programmed, spi prog. enabled) wdton (3) 4 watchdog timer always on 1 (unprogrammed) eesave 3 eeprom memory is preserved through the chip erase 1 (unprogrammed, eeprom not preserved) bootsz1 2 select boot size (see table 27-9 on page 259 for details) 0 (programmed) (2) bootsz0 1 select boot size (see table 27-9 on page 259 for details) 0 (programmed) (2) bootrst 0 select re set vector 1 (unprogrammed) notes: 1. the spien fuse is not accessible in serial programming mode. 2. the default value of bootsz1..0 results in maximum boot size. see table 26-10 on page 251 for details. 3. see section 11.4.2 ?wdtcsr ? watchdog timer control register? on page 47 for details. 4. never ship a product with the ocden fuse programmed regardless of the setting of lock bits and jtagen fuse. a programmed ocden fuse enables some parts of the clock system to be runn ing in all sleep modes. this may increase the power consumption. table 27-5. fuse low byte fuse low byte bit no description default value ckdiv8 (4) 7 divide clock by 8 0 (programmed) ckout (3) 6 clock output 1 (unprogrammed) sut1 5 select start-up time 1 (unprogrammed) (1) sut0 4 select start-up time 0 (programmed) (1) cksel3 3 select clock source 0 (programmed) (2) cksel2 2 select clock source 0 (programmed) (2) cksel1 1 select clock source 1 (unprogrammed) (2) cksel0 0 select clock source 0 (programmed) (2) notes: 1. the default value of sut1..0 results in maxi mum start-up time for the default clock source. see section 28.5 ?system and reset characteristics? on page 291 for details. 2. the default setting of cksel3..0 results in internal rc oscillator at 8mhz. see table 9-1 on page 24 for details. 3. the ckout fuse allow the system clock to be output on portb1. see section 9.10 ?clock output buffer? on page 31 for details. 4. see section 9.11 ?system clock prescaler? on page 31 for details. atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 258 27.3 signature bytes all atmel ? microcontrollers have a three-byte signat ure code which identifies the device. th is code can be read in both serial and parallel mode, also when the device is locked. the three bytes reside in a separate address space. for the atmel atmega164p-b/324p-b/644p-b the signature bytes are given in table 27-6 . 27.4 calibration byte the atmel atmega164p-b/324p-b/644p-b has a byte 2 calibration va lues for the internal rc oscillator. the 3v calibration byte resides in the address 0x0001 in the signature address space and the 5v calibration byte resides in the address 0x0003. during reset, the 3v calibration byte is automatically written into the osccal register to ensure correct frequency of the calibrated rc oscillator. 27.5 page size table 27-6. device and jtag id part signature bytes address jtag 0x000 0x001 0x002 part number manufacture id atmega164p-b 0x1e 0x94 0x0a 940a 0x1f atmega324p-b 0x1e 0x95 0x11 9511 0x1f atmega644p-b 0x1e 0x96 0x0a 960a 0x1f table 27-7. no. of words in a page and no. of pages in the flash device flash size page size pcword no. of pages pcpage pcmsb atmega164p-b 8k words (16kbytes) 64 words pc[5:0] 128 pc[12:6] 12 atmega324p-b 16k words (32kbytes) 64 words pc[5:0] 256 pc[13:6] 13 atmega644p-b 32k words (64kbytes) 128 words pc[6:0] 256 pc[14:6] 14 table 27-8. no. of words in a page and no. of pages in the eeprom device eeprom size page size pcword no. of pages pcpage eeamsb atmega164p-b 512bytes 4 bytes eea[1:0] 128 eea[8:2] 8 atmega324p-b 1kbytes 4 bytes eea[1:0] 256 eea[9:2] 9 atmega644p-b 2kbytes 8 bytes eea[2:0] 256 eea[10:2] 10 259 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 27.6 parallel programming parameters, pin mapping, and commands this section describes how to parallel progr am and verify flash program memory, eeprom data memory, memory lock bits, and fuse bits in the atmel atm ega164p-b/324p-b/644p-b. pulses are assumed to be at least 250ns unless otherwise noted. 27.6.1 signal names in this section, some pins of the atmel atmega164p-b/324p -b/644p-b are referenced by signal names describing their functionality during parallel programming, see figure 27-1 and figure 27-9 on page 259 . pins not described in the following table are referenced by pin names. the xa1/xa0 pins determine the action executed when the xta l1 pin is given a positive pulse. the bit coding is shown in table 27-12 on page 260 . when pulsing wr or oe , the command loaded determines the action exec uted. the different commands are shown in table 27-13 on page 260 . figure 27-1. parallel programming (1) note: 1. unused pins should be left floating. table 27-9. pin name mapping signal name in programming mode pin name i/o function rdy/bsy pd1 o 0: device is busy programming, 1: device is ready for new command. oe pd2 i output enable (active low). wr pd3 i write pulse (active low). bs1 pd4 i byte select 1. xa0 pd5 i xtal action bit 0 xa1 pd6 i xtal action bit 1 pagel pd7 i program memory and eeprom data page load. bs2 pa0 i byte select 2. data pb7-0 i/o bi-directional data bus (output when oe is low). gnd xtal1 pa 0 pd1 pd2 pd3 pd4 data pd5 pd6 pd7 reset vcc avcc pb7 to pb0 + 5v + 5v rdy/bsy oe wr bs1 xa0 xa1 pagel +12v bs2 atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 260 , table 27-10. bs2 and bs1 encoding bs2 bs1 flash / eeprom address flash data loading / reading fuse programming reading fuse and lock bits 0 0 low byte low byte low byte fuse low byte 0 1 high byte high byte high byte lock bits 1 0 extended high byte reserved extended byte extended fuse byte 1 1 reserved reserved reserved fuse high byte table 27-11. pin values used to enter programming mode pin symbol value pagel prog_enable[3] 0 xa1 prog_enable[2] 0 xa0 prog_enable[1] 0 bs1 prog_enable[0] 0 table 27-12. xa1 and xa0 encoding xa1 xa0 action when xtal1 is pulsed 0 0 load flash or eeprom addre ss (high or low address by te determined by bs2 and bs1) 0 1 load data (high or low data byte for flash determined by bs1) 1 0 load command 1 1 no action, idle table 27-13. command byte bit encoding command byte command executed 1000 0000 chip erase 0100 0000 write fuse bits 0010 0000 write lock bits 0001 0000 write flash 0001 0001 write eeprom 0000 1000 read signature bytes and calibration byte 0000 0100 read fuse and lock bits 0000 0010 read flash 0000 0011 read eeprom 261 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 27.7 parallel programming 27.7.1 enter programming mode the following algorithm puts the device in parallel programming mode: 1. apply 4.5 - 5.5v between v cc and gnd. 2. set reset to ?0? and toggle xtal1 at least six times. 3. set the prog_enable pins listed in table 27-11 on page 260 to ?0000? and wait at least 100ns. 4. apply 11.5 - 12.5v to reset . any activity on prog_enable pins within 100ns after +12v has been applied to reset , will cause the device to fail entering programming mode. 5. wait at least 50s before sending a new command. 27.7.2 considerations for efficient programming the loaded command and address are retained in the device dur ing programming. for efficient programming, the following should be considered. the command needs only be loaded once when writing or reading multiple memory locations. skip writing the data value 0xff, that is the contents of the entire eeprom (unless the eesave fuse is programmed) and flash after a chip erase. address high byte needs only be loaded before programming or reading a new 256 word window in flash or 256 byte eeprom. this consideration also applies to signature bytes reading. 27.7.3 chip erase the chip erase will er ase the flash and eeprom (1) memories plus lock bits. the lock bits are not reset until the program memory has been completely erased. the fuse bits are no t changed. a chip erase must be performed before the flash and/or eeprom are reprogrammed. note: 1. the eeprpom memory is preserved during chip erase if the eesave fuse is programmed. load command ?chip erase? 1. set xa1, xa0 to ?10?. this enables command loading. 2. set bs1 to ?0?. 3. set data to ?1000 0000?. this is the command for chip erase. 4. give xtal1 a positive pulse. this loads the command. 5. give wr a negative pulse. this star ts the chip erase. rdy/bsy goes low. 6. wait until rdy/bsy goes high before loading a new command. atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 262 27.7.4 programming the flash the flash is organized in pages, see table 27-7 on page 258 . when programming the flash, t he program data is latched into a page buffer. this allows one page of program data to be programmed simultaneously. the following procedure describes how to program the entire flash memory: a. load command ?write flash? 1. set xa1, xa0 to ?10?. this enables command loading. 2. set bs1 to ?0?. 3. set data to ?0001 0000?. this is the command for write flash. 4. give xtal1 a positive pulse. this loads the command. b. load address low byte (address bits 7..0) 1. set xa1, xa0 to ?00?. this enables address loading. 2. set bs2, bs1 to ?00?. this selects the address low byte. 3. set data = address low byte (0x00 - 0xff). 4. give xtal1 a positive pulse. this loads the address low byte. c. load data low byte 1. set xa1, xa0 to ?01?. this enables data loading. 2. set data = data low byte (0x00 - 0xff). 3. give xtal1 a positive pulse. this loads the data byte. d. load data high byte 1. set bs1 to ?1?. this selects high data byte. 2. set xa1, xa0 to ?01?. this enables data loading. 3. set data = data high byte (0x00 - 0xff). 4. give xtal1 a positive pulse. this loads the data byte. e. latch data 1. set bs1 to ?1?. this selects high data byte. 2. give pagel a positive pulse. this latches the data bytes. (see figure 27-3 on page 263 for signal waveforms) f. repeat b through e until the entire buffer is filled or until all data within the page is loaded. while the lower bits in the address are mapped to words wi thin the page, the higher bits address the pages within the flash. this is illustrated in figure 27-2 on page 263 . note that if less than eight bits are required to address words in the page (page size < 256), the most significant bit(s) in the a ddress low byte are used to address the page when performing a page write. g. load address high byte (address bits15..8) 1. set xa1, xa0 to ?00?. this enables address loading. 2. set bs2, bs1 to ?01?. this selects the address high byte. 3. set data = address high byte (0x00 - 0xff). 4. give xtal1 a positive pulse. this loads the address high byte. h. load address extended high byte (address bits 23..16) 1. set xa1, xa0 to ?00?. this enables address loading. 2. set bs2, bs1 to ?10?. this selects the address extended high byte. 3. set data = address extended high byte (0x00 - 0xff). 4. give xtal1 a positive pulse. this loads the address high byte. i. program page 1. set bs2, bs1 to ?00? 2. give wr a negative pulse. this starts programm ing of the entire page of data. rdy/bsy goes low. 3. wait until rdy/bsy goes high (see figure 27-3 on page 263 for signal waveforms). 263 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 j. repeat b through i until the entire flash is programmed or until all data has been programmed. k. end page programming 1. 1. set xa1, xa0 to ?10?. this enables command loading. 2. set data to ?0000 0000?. this is the command for no operation. 3. give xtal1 a positive pulse. this loads the co mmand, and the internal write signals are reset. figure 27-2. addressing the flash which is organized in pages (1) note: 1. pcpage and pcword are listed in table 27-7 on page 258 . figure 27-3. programming the flash waveforms (1) note: 1. ?xx? is don?t care. the letters re fer to the programming description above. pagemsb pcmsb program counter word address within page page address within the flash pcword pcpage 02 01 00 pageend pcword [pagemsb : 0] page program memory instructions word page 0x10 addr. low ab data xa1 xa0 bs1 bs2 xtal1 wr pagel rdy/bsy oe reset +12v data low data high cd addr. low b data low data high cd f xx e xx e xx i addr. high g addr.ext.h h atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 264 27.7.5 programming the eeprom the eeprom is organized in pages, see table 27-8 on page 258 . when programming the eeprom, the program data is latched into a page buffer. this allows one page of data to be programmed simultaneously. the programming algorithm for the eeprom data memory is as follows (refer to section 27.7.4 ?programming the flash? on page 262 for details on command, address and data loading): 1. a: load command ?0001 0001?. 2. g: load address high byte (0x00 - 0xff). 3. b: load address low byte (0x00 - 0xff). 4. c: load data (0x00 - 0xff). 5. e: latch data (give pagel a positive pulse). k: repeat 3 through 5 until the entire buffer is filled. l: program eeprom page 1. set bs2, bs1 to ?00?. 2. give wr a negative pulse. this starts pr ogramming of the eeprom page. rdy/bsy goes low. 3. wait until to rdy/bsy goes high before programming the next page (see figure 27-4 for signal waveforms). figure 27-4. programming the eeprom waveforms 0x11 ag data xa1 xa0 bs1 bs2 xtal1 wr pagel rdy/bsy oe reset +12v bc addr. low addr. low b data xx ce k xx data el addr. high 265 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 27.7.6 reading the flash the algorithm for reading the flash memory is as follows (refer to section 27.7.4 ?programmi ng the flash? on page 262 for details on command and address loading): 1. a: load command ?0000 0010?. 2. h: load address extended byte (0x00- 0xff). 3. g: load address high byte (0x00 - 0xff). 4. b: load address low byte (0x00 - 0xff). 5. set oe to ?0?, and bs1 to ?0?. the flash word low byte can now be read at data. 6. set bs to ?1?. the flash word high byte can now be read at data. 7. set oe to ?1?. 27.7.7 reading the eeprom the algorithm for reading the eeprom memory is as follows (refer to section 27.7.4 ?programming the flash? on page 262 for details on command and address loading): 1. a: load command ?0000 0011?. 2. g: load address high byte (0x00 - 0xff). 3. b: load address low byte (0x00 - 0xff). 4. set oe to ?0?, and bs1 to ?0?. the eeprom data byte can now be read at data. 5. set oe to ?1?. 27.7.8 programming the fuse low bits the algorithm for programming the fuse low bits is as follows (refer to section 27.7.4 ?programming the flash? on page 262 for details on command and data loading): 1. a: load command ?0100 0000?. 2. c: load data low byte. bit n = ?0? programs and bit n = ?1? erases the fuse bit. 3. give wr a negative pulse and wait for rdy/bsy to go high. 27.7.9 programming the fuse high bits the algorithm for programming the fuse high bits is as follows (refer to section 27.7.4 ?programming the flash? on page 262 for details on command and data loading): 1. a: load command ?0100 0000?. 2. c: load data low byte. bit n = ?0? programs and bit n = ?1? erases the fuse bit. 3. set bs2, bs1 to ?01?. this selects high data byte. 4. give wr a negative pulse and wait for rdy/bsy to go high. 5. set bs2, bs1 to ?00?. this selects low data byte. 27.7.10 programming the extended fuse bits the algorithm for programming the extended fuse bits is as follows (refer to 27.7.4 ?programming the flash? on page 262 for details on command and data loading): 1. 1. a: load command ?0100 0000?. 2. 2. c: load data low byte. bit n = ?0? progr ams and bit n = ?1? erases the fuse bit. 3. 3. set bs2, bs1 to ?10?. this selects extended data byte. 4. 4. give wr a negative pulse and wait for rdy/bsy to go high. 5. 5. set bs2, bs1 to ?00?. this selects low data byte. atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 266 figure 27-5. programmi ng the fuses waveforms 27.7.11 programming the lock bits the algorithm for programming the lock bits is as follows (refer to section 27.7.4 ?programming the flash? on page 262 for details on command and data loading): 1. a: load command ?0010 0000?. 2. c: load data low byte. bit n = ?0? programs the lock bit. if lb mode 3 is programmed (lb1 and lb2 is programmed), it is not possible to program the bo ot lock bits by any external programming mode. 3. give wr a negative pulse and wait for rdy/bsy to go high. the lock bits can only be cleared by executing chip erase. 27.7.12 reading the fuse and lock bits the algorithm for reading the fuse and lock bits is as follows (refer to section 27.7.4 ?programming the flash? on page 262 for details on command loading): 1. a: load command ?0000 0100?. 2. set oe to ?0?, and bs2, bs1 to ?00?. the status of the fuse low bits can now be read at data (?0? means programmed). 3. set oe to ?0?, and bs2, bs1 to ?11?. the status of the fuse high bits can now be read at data (?0? means programmed). 4. set oe to ?0?, and bs2, bs1 to ?10?. the status of the extended fuse bits can now be read at data (?0? means programmed). 5. set oe to ?0?, and bs2, bs1 to ?01?. the status of the lock bits can now be read at data (?0? means programmed). 6. set oe to ?1?. 0x40 ac data xa1 xa0 bs1 bs2 xtal1 wr pagel rdy/bsy oe reset +12v 0x40 0x40 data a data xx c write fuse low byte write fuse high byte write extended fuse byte xx data a xx c 267 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 figure 27-6. mapping between bs1, bs2 an d the fuse and lock bits during read 27.7.13 reading the signature bytes the algorithm for reading the signature bytes is as follows (refer to section 27.7.4 ?programming the flash? on page 262 for details on command and address loading): 1. a: load command ?0000 1000?. 2. b: load address low byte (0x00 - 0x02). 3. set oe to ?0?, and bs to ?0?. the selected signature byte can now be read at data. 4. set oe to ?1?. 27.7.14 reading the calibration byte the algorithm for reading the calibratio n byte is as follows (refer to section 27.7.4 ?programming the flash? on page 262 for details on command and address loading): 1. a: load command ?0000 1000?. 2. b: load address low byte, 0x00. 3. set oe to ?0?, and bs1 to ?1?. the calibration byte can now be read at data. 4. set oe to ?1?. extended fuse byte 0 1 fuse low byte bs2 fuse high byte 0 1 lock bits bs2 bs1 data 0 1 atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 268 27.7.15 parallel prog ramming characteristics figure 27-7. parallel programming timing, in cluding some general timing requirements table 27-14. parallel progra mming characteristics, v cc = 5v 10% parameter symbol min typ. max unit programming enable voltage v pp 11.5 12.5 v programming enable current i pp 250 a data and control valid before xtal1 high t dvxh 67 ns xtal1 low to xtal1 high t xlxh 200 ns xtal1 pulse width high t xhxl 150 ns data and control hold after xtal1 low t xldx 67 ns xtal1 low to wr low t xlwl 0 ns xtal1 low to pagel high t xlph 0 ns pagel low to xtal1 high t plxh 150 ns bs1 valid before pagel high t bvph 67 ns pagel pulse width high t phpl 150 ns bs1 hold after pagel low t plbx 67 ns bs2/1 hold after wr low t wlbx 67 ns pagel low to wr low t plwl 67 ns bs2/1 valid to wr low t bvwl 67 ns wr pulse width low t wlwh 150 ns wr low to rdy/bsy low t wlrl 0 1 s wr low to rdy/bsy high (1) t wlrh 3.7 4.5 ms wr low to rdy/bsy high for chip erase (2) t wlrh_ce 7.5 9 ms xtal1 low to oe low t xlol 0 ns bs1 valid to data valid t bvdv 0 250 ns oe low to data valid t oldv 250 ns oe high to data tri-stated t ohdz 250 ns notes: 1. t wlrh is valid for the write flash, write eeprom, write fuse bits and write lock bits commands. 2. t wlrh_ce is valid for the chip erase command. xtal1 pagel wr data and control (data, xa0/1, bs1, bs2) t xhxl t dvxh t bvph t xlwl t xldx t phpl t plbx t plwl t bvwl t wlbx t wlwh t wlrl t wlrh rdy/bsy 269 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 figure 27-8. parallel programming timing, loading sequence with timing requirements (1) note: the timing requirements shown in figure 27-7 on page 268 (i.e., t dvxh , t xhxl , and t xldx ) also apply to loading operation. figure 27-9. parallel programming timing, reading sequence (within the same page) with timing requirements (1) note: 1. the timing requirements shown in table 27-7 on page 268 (i.e., t dvxh , t xhxl , and t xldx ) also apply to reading operation. xtal1 bs1 pagel data xa0 xa1 t xlxh t plxh t xlph load address (low byte) load data (low byte) load data (high byte) load address (low byte) load data addr0 (low byte) addr1 (low byte) data (low byte) data (high byte) xtal1 bs1 oe data xa0 xa1 t bvdv t xlol t oldv t ohdz load address (low byte) read data (low byte) read data (high byte) load address (low byte) addr0 (low byte) addr1 (low byte) data (low byte) data (high byte) atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 270 27.8 serial downloading both the flash and eeprom memory arrays can be programmed using a serial programming bus while reset is pulled to gnd. the serial programming interface consists of pi ns sck, mosi (input) and miso (output). after reset is set low, the programming enable instruction needs to be executed first be fore program/erase operations can be executed. note, in table 27-15 , the pin mapping for serial programming is listed. not a ll packages use the spi pins dedicated for the internal serial peripheral interface - spi. 27.8.1 serial programming pin mapping figure 27-10. serial programming and verify (1) notes: 1. if the device is clocked by the internal oscillator, it is no need to connect a clock source to the xtal1 pin. 2. v cc ? 0.3v < avcc < v cc + 0.3v, however, avcc should always be within 2.7 to 5.5v when programming the eeprom, an auto-erase cycle is built into the self-timed programming operation (in the serial mode only) and there is no need to first execute the chip erase inst ruction. the chip erase operat ion turns the content of every memory location in bo th the program and eepr om arrays into 0xff. depending on cksel fuses, a vali d clock must be present. the minimum low an d high periods for the serial clock (sck) input are defined as follows: low: > 2 cpu clock cycles for f ck < 12mhz, 3 cpu clock cycles for f ck 12mhz high: > 2 cpu clock cycles for f ck < 12mhz, 3 cpu clock cycles for f ck 12mhz table 27-15. pin mapping serial programming symbol pins (pdip-40) pins (tqfp/mlf-44) i/o description mosi pb5 pb5 i serial data in miso pb6 pb6 o serial data out sck pb7 pb7 i serial clock gnd xtal1 reset vcc avcc + 2.7v to 5.5v + 2.7v to 5.5v (2) mosi miso sck 271 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 27.8.2 serial programming algorithm when writing serial data to the atmel ? atmega164p-b/324p-b/644p-b, data is clocked on the rising edge of sck. when reading data from the atmel atm ega164p-b/324p-b/644p-b, data is clo cked on the falling edge of sck. see figure 27-12 on page 273 for timing details. to program and verify the atmega164p-b/ 324p-b/644p-b in the serial programmi ng mode, the following sequence is recommended (see four byte instruction formats in table 27-17 on page 272 ): 1. power-up sequence: apply power between v cc and gnd while reset and sck are set to ?0?. in so me systems, the programmer can not guarantee that sck is held low dur ing power-up. in this case, reset must be given a positive pulse of at least two cpu clock cycles durati on after sck has been set to ?0?. 2. wait for at least 20ms and enable serial programming by sending the programming enable serial instruction to pin mosi. 3. the serial programming instructions will not work if t he communication is out of syn chronization. when in sync. the second byte (0x53), will echo back when issuing the thir d byte of the programming enable instruction. whether the echo is correct or not, all four byte s of the instruction must be transmitt ed. if the 0x53 did not echo back, give reset a positive pulse and issue a new programming enable command. 4. the flash is programmed one page at a time. the memory page is loaded one byte at a time by supplying the 7 lsb of the address and data together wi th the load program memory page instruction. to ensure correct loading of the page, the data low byte must be loaded before dat a high byte is applied for a given address. the program memory page is stored by loading the write program memory page instructi on with the address lines 15.8. before issuing this command, make sure the instruction load extended address byte has be en used to define the msb of the address. the extended address byte is stored unt il the command is re-issued, i.e., the command needs only be issued for the first page, and when crossi ng the 64kword boundary. if polling (rdy/bsy ) is not used, the user must wait at least t wd_flash before issuing the next page. (see table 27-16 on page 271 .) accessing the serial programming interface before the fl ash write operation completes can result in incorrect programming. 5. the eeprom array is programmed one byte at a time by supplying the address and data together with the appropriate write instruction. an eeprom memory loca tion is first automatically erased before new data is written. if polling is not used, the user must wait at least t wd_eeprom before issuing the next byte. (see table 27-16 on page 271 .) in a chip erased device, no 0xffs in the data file(s) need to be programmed. 6. any memory location can be verified by using the read instruction which returns the content at the selected address at serial output miso. when reading the flash me mory, use the instruction load extended address byte to define the upper address byte, which is not included in the read program memory instruction. the extended address byte is stored until the command is re-issued, i.e ., the command needs only be issued for the first page, and when crossing the 64kword boundary. 7. at the end of the programming session, reset can be set high to commence normal operation. 8. power-off sequence (if needed): set reset to ?1?. turn v cc power off. table 27-16. minimum wait delay before wr iting the next flash or eeprom location symbol minimum wait delay t wd_flash 4.5ms t wd_eeprom 3.6ms t wd_erase 9.0ms atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 272 27.9 serial programming instruction set table 27-17 and figure 27-11 on page 273 describes the instruction set. table 27-17. serial programming instruction set (hexadecimal values) instruction/operation instruction format byte 1 byte 2 byte 3 byte4 programming enable $ac $53 $00 $00 chip erase (program memory/eeprom) $ac $80 $00 $00 poll rdy/bsy $f0 $00 $00 data byte out load instructions load extended address byte (1) $4d $00 extended adr $00 load program memory page, high byte $48 $00 adr lsb high data byte in load program memory page, low byte $40 $00 adr lsb low data byte in load eeprom memory page (page access) $c1 $00 0000 000aa data byte in read instructions read program memory, high byte $28 adr msb adr lsb high data byte out read program memory, low byte $20 adr msb adr lsb low data byte out read eeprom memory $a0 0000 00aa aaaa aaaa data byte out read lock bits $58 $00 $00 data byte out read signature byte $30 $00 0000 000aa data byte out read fuse bits $50 $00 $00 data byte out read fuse high bits $58 $08 $00 data byte out read extended fuse its $50 $08 $00 data byte out read calibration byte $38 $00 $00 data byte out write instructions (6) write program memory page $4c adr msb adr lsb $00 write eeprom memory $c0 0000 00aa aaaa aaaa data byte in write eeprom memory page (page access) $c2 0000 00aa aaaa aa00 $00 write lock bits $ac $e0 $00 data byte in write fuse bits $ac $a0 $00 data byte in write fuse high bits $ac $a8 $00 data byte in write extended fuse bits $ac $a4 $00 data byte in notes: 1. not all instructions are applicable for all parts. 2. a = address. 3. bits are programmed ?0?, unprogrammed ?1?. 4. to ensure future compatibility, unused fuses and lock bits should be unprogrammed (?1?). 5. refer to the corresponding section for fuse and lock bits, calibration and signature bytes and page size. 6. instructions accessing program memory use a word address. this address may be random within the page range. 7. see http://www.atmel.com/avr for application notes regarding programming and programmers. 273 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 if the lsb in rdy/bsy data byte out is ?1?, a programming oper ation is still pending. wait until this bit returns ?0? before th e next instruction is carried out. within the same page, the low data byte must be loaded prior to the high data byte. after data is loaded to the page buffer, program the eeprom page, see figure 27-11 on page 273 . figure 27-11. serial progra mming instruction example 27.9.1 serial progra mming characteristics for characteristics of the serial programming module see section 28.7 ?spi timing characteristics? on page 292 . figure 27-12. serial programming waveforms byte 1 byte 2 byte 3 byte 4 page 0 page 1 page 2 adr lbs adr mbs bit 15 b 0 bit 15 b 0 byte 1 byte 2 byte 3 byte 4 adr lbs adr mbs page n-1 program memory / eeprom memory serial programming instruction page buffer page number page offset load program memory page (high/low byte)/ load eeprom memory page (page access) write program memory page / write eeprom memory page serial data input (mosi) serial data output (miso) serial clock input (sck) sample msb lsb msb lsb atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 274 27.10 programming via the jtag interface programming through the jtag interface r equires control of the four jtag specific pins: tck, tms, tdi, and tdo. control of the reset and clock pins is not required. to be able to use the jtag interface, the jtagen fuse mu st be programmed. the device is default shipped with the fuse programmed. in addition, the jtd bit in mcucr must be cleared. al ternatively, if the jtd bit is set, the external reset can be forced low. then, the jtd bit will be cleared after two chip cl ocks, and the jtag pins are available for programming. this provides a means of using the jt ag pins as normal port pins in running mode while still al lowing in-system programming via the jtag interface. note that this technique can not be used when using the jtag pins for boundary-scan or on-chip debug. in these cases the jtag pins must be dedicated for this purpose. during programming the clock frequency of the tck input mu st be less than the maximum frequency of the chip. the system clock prescaler can no t be used to divide the tck clock input into a sufficiently low frequency. as a definition in this datasheet, the lsb is shifted in and out first of all shift registers. 27.10.1 programming specific jtag instructions the instruction register is 4-bit wide, supporting up to 16 inst ructions. the jtag instructions useful for programming are listed below. the opcode for each instruction is show n behind the instruction name in hex format. the text describes which data register is selected as path betwe en tdi and tdo for each instruction. the run-test/idle state of the tap controller is used to gener ate internal clocks. it can also be used as an idle state between jtag sequences. the state machine sequence fo r changing the instruction word is shown in figure 27-13 on page 275 . 275 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 figure 27-13. state machine sequence for changing the instruction word 27.10.2 avr_reset (0xc) the avr ? specific public jtag instruction for setting the avr devi ce in the reset mode or taki ng the device out from the reset mode. the tap cont roller is not reset by this instruction. the one bit reset register is selected as data register. note that the reset will be active as long as there is a logic ?one? in the reset chain. the output from this chain is not latched. the active states are: shift-dr: the reset register is shifted by the tck input. 27.10.3 prog_enable (0x4) the avr specific public jtag instruction for enabling pr ogramming via the jtag port. the 16-bit programming enable register is selected as data register . the active states are the following: shift-dr: the programming enable signature is shifted into the data register. update-dr: the programming enable si gnature is compared to the correct va lue, and programming mode is entered if the signature is valid. test logic reset run test/idle select ir scan select dr scan capture ir capture dr 0 00 00 00 shift ir shift dr 11 exit1 ir exit1 dr exit2 ir exit2 dr 00 pause ir pause dr 11 update ir update dr 1 10 10 1 1 00 0 1 1 0 1 0 11 1 1 atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 276 27.10.4 prog_co mmands (0x5) the avr ? specific public jtag instruction for entering programming commands via the jtag port. the 15-bit programming command register is selected as data re gister. the active states are the following: capture-dr: the result of the previous co mmand is loaded into the data register. shift-dr: the data register is shifted by the tck input, shif ting out the result of the previous command and shifting in the new command. update-dr: the programming command is applied to the flash inputs run-test/idle: one clock cycle is genera ted, executing the applied command 27.10.5 prog_pageload (0x6) the avr specific public jtag instruction to directly load t he flash data page via the jtag port. an 8-bit flash data byte register is selected as the dat a register. this is physically the 8 lsbs of the programming command register. the active states are the following: shift-dr: the flash data byte regist er is shifted by the tck input. update-dr: the content of the flash data byte register is copied into a temporary r egister. a write sequence is initiated that withi n 11 tck cycles loads the content of the temporary register in to the flash page buffer. the avr automatically alternates betw een writing the low and the high byte for ea ch new update-dr state, starting with the low byte for the first update-dr encountered after entering the prog_pageload command. the program counter is pre-incremented before writing the low byte, except for the firs t written byte. this ensures that the first data is written to the address set up by prog_commands, and loading the last location in the page buffer does not make the program counter increment into the next page. 27.10.6 prog_pageread (0x7) the avr specific public jtag instruction to directly capture the flash content via the jtag port. an 8-bit flash data byte register is selected as the dat a register. this is physically the 8 lsbs of the programming command register. the active states are the following: capture-dr: the content of the select ed flash byte is captured into the flash data byte register. the avr automatically alternates between reading the low and the high byte for ea ch new capture-dr state, starting with the low byte for the first capture-dr encountered after ent ering the prog_pageread command. the program counter is post-incremented after reading each high byte, including the first read byte. this ensures that the first data is captured from the first address set up by prog_commands , and reading the last location in the page makes the program counter increment into the next page. shift-dr: the flash data byte regist er is shifted by the tck input. 27.10.7 data registers the data registers are selected by the jtag instruction registers described in section section 27.10.1 ?programming specific jtag instructions? on page 274 . the data registers relevant for programming operations are: reset register programming enable register programming command register flash data byte register 277 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 27.10.8 reset register the reset register is a test data register used to reset th e part during programming. it is required to reset the part before entering programming mode. a high value in the reset register corresponds to pulling the extern al reset low. the part is reset as long as there is a high value present in the reset register. depending on the fuse setti ngs for the clock options, the part will remain reset for a res et time-out period (refer to section 9.2 ?clock sources? on page 24 ) after releasing the reset register. the output from this data register is not latched, so the reset wil l take place immediately, as shown in figure 25-2 on page 232 . 27.10.9 programming enable register the programming enable register is a 16-bi t register. the contents of this regist er is compared to the programming enable signature, binary code 0b1010_0011_0111_0000. when the contents of the register is equal to the programming enable signature, programming via the jtag port is enabled. the regist er is reset to 0 on power-on reset, and should always be reset when leaving programming mode. figure 27-14. programming enable register 0xa370 programming enable clockdr and prog_enable d a t a tdi tdo d = q atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 278 27.10.10 programming command register the programming command register is a 15-bit register. this register is used to se rially shift in programming commands, and to serially shift out the result of the previous command , if any. the jtag programming instruction set is shown in table 27-18 on page 279 . the state sequence when shifting in the programming commands is illustrated in figure 27-16 on page 282 . figure 27-15. programming command register flash eeprom fuses lock bits s t r o b e s a d d r e s s / d a t a tdi tdo 279 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 table 27-18. jtag programming instruction set a = address high bits, b = address low bits, c = address extended bits, h = 0 - low byte, 1 - high byte, o = data out, i = data in, x = don?t care instruction tdi sequence tdo sequence notes 1a. chip erase 0100011_10000000 0110001_10000000 0110011_10000000 0110011_10000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx 1b. poll for chip erase complete 0110011_10000000 xxxxxox_xxxxxxxx (2) 2a. enter flash write 0100011_00010000 xxxxxxx_xxxxxxxx 2b. load address extended high byte 0001011_cccccccc xxxxxxx_xxxxxxxx (10) 2c. load address high byte 0000111_aaaaaaaa xxxxxxx_xxxxxxxx 2d. load address low byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx 2e. load data low byte 0010011_iiiiiiii xxxxxxx_xxxxxxxx 2f. load data high byte 0010111_iiiiiiii xxxxxxx_xxxxxxxx 2g. latch data 0110111_00000000 1110111_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (1) 2h. write flash page 0110111_00000000 0110101_00000000 0110111_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (1) 2i. poll for page write complete 0110111_00000000 xxxxxox_xxxxxxxx (2) 3a. enter flash read 0100011_00000010 xxxxxxx_xxxxxxxx 3b. load address extended high byte 0001011_cccccccc xxxxxxx_xxxxxxxx (10) 3c. load address high byte 0000111_aaaaaaaa xxxxxxx_xxxxxxxx 3d. load address low byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx 3e. read data low and high byte 0110010_00000000 0110110_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_oooooooo xxxxxxx_oooooooo low byte high byte 4a. enter eeprom write 0100011_00010001 xxxxxxx_xxxxxxxx 4b. load address high byte 0000111_aaaaaaaa xxxxxxx_xxxxxxxx (10) 4c. load address low byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx 4d. load data byte 0010011_iiiiiiii xxxxxxx_xxxxxxxx notes: 1. this command sequence is not required if the seven msb are correctly set by the previous command sequence (which is normally the case). 2. repeat until o = ?1?. 3. set bits to ?0? to program the corre sponding fuse, ?1? to unprogram the fuse. 4. set bits to ?0? to program the corresponding lock bit, ?1? to leave the lock bit unchanged. 5. ?0? = programmed, ?1? = unprogrammed. 6. the bit mapping for fuses extended byte is listed in table 27-3 on page 256 7. the bit mapping for fuses high byte is listed in table 27-4 on page 257 8. the bit mapping for fuses low byte is listed in table 27-5 on page 257 9. the bit mapping for lock bits byte is listed in table 27-1 on page 255 10. address bits exceeding pcmsb and eeamsb ( table 27-7 on page 258 and table 27-8 on page 258 ) are don?t care 11. all tdi and tdo sequences are represented by binary digits (0b...). atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 280 4e. latch data 0110111_00000000 1110111_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (1) 4f. write eeprom page 0110011_00000000 0110001_00000000 0110011_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (1) 4g. poll for page write complete 0110011_00000000 xxxxxox_xxxxxxxx (2) 5a. enter eeprom read 0100011_00000011 xxxxxxx_xxxxxxxx 5b. load address high byte 0000111_aaaaaaaa xxxxxxx_xxxxxxxx (10) 5c. load address low byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx 5d. read data byte 0110011_bbbbbbbb 0110010_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_oooooooo 6a. enter fuse write 0100011_01000000 xxxxxxx_xxxxxxxx 6b. load data low byte (6) 0010011_iiiiiiii xxxxxxx_xxxxxxxx (3) 6c. write fuse extended byte 0111011_00000000 0111001_00000000 0111011_00000000 0111011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (1) 6d. poll for fuse write complete 0110111_00000000 xxxxxox_xxxxxxxx (2) 6e. load data low byte (7) 0010011_iiiiiiii xxxxxxx_xxxxxxxx (3) 6f. write fuse high byte 0110111_00000000 0110101_00000000 0110111_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (1) 6g. poll for fuse write complete 0110111_00000000 xxxxxox_xxxxxxxx (2) 6h. load data low byte (7) 0010011_iiiiiiii xxxxxxx_xxxxxxxx (3) 6i. write fuse low byte 0110011_00000000 0110001_00000000 0110011_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (1) 6j. poll for fuse write complete 0110011_00000000 xxxxxox_xxxxxxxx (2) table 27-18. jtag programming instruction (continued) set a = address high bits, b = address low bits, c = address extended bits, h = 0 - low byte, 1 - high byte, o = data out, i = data in, x = don?t care instruction tdi sequence tdo sequence notes notes: 1. this command sequence is not required if the seven msb are correctly set by the previous command sequence (which is normally the case). 2. repeat until o = ?1?. 3. set bits to ?0? to program the corre sponding fuse, ?1? to unprogram the fuse. 4. set bits to ?0? to program the corresponding lock bit, ?1? to leave the lock bit unchanged. 5. ?0? = programmed, ?1? = unprogrammed. 6. the bit mapping for fuses extended byte is listed in table 27-3 on page 256 7. the bit mapping for fuses high byte is listed in table 27-4 on page 257 8. the bit mapping for fuses low byte is listed in table 27-5 on page 257 9. the bit mapping for lock bits byte is listed in table 27-1 on page 255 10. address bits exceeding pcmsb and eeamsb ( table 27-7 on page 258 and table 27-8 on page 258 ) are don?t care 11. all tdi and tdo sequences are represented by binary digits (0b...). 281 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 7a. enter lock bit write 0100011_00100000 xxxxxxx_xxxxxxxx 7b. load data byte (9) 0010011_11 iiiiii xxxxxxx_xxxxxxxx (4) 7c. write lock bits 0110011_00000000 0110001_00000000 0110011_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (1) 7d. poll for lock bit write complete 0110011_00000000 xxxxxox_xxxxxxxx (2) 8a. enter fuse/lock bit read 0100011_00000100 xxxxxxx_xxxxxxxx 8b. read extended fuse byte (6) 0111010_00000000 0111011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_oooooooo 8c. read fuse high byte (7) 0111110_0 0000000 0111111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_oooooooo 8d. read fuse low byte (8) 0110010_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_oooooooo 8e. read lock bits (9) 0110110_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxoooooo (5) 8f. read fuses and lock bits 0111010_00000000 0111110_0 0000000 0110010_00000000 0110110_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_oooooooo xxxxxxx_oooooooo xxxxxxx_oooooooo xxxxxxx_oooooooo (5) fuse ext. byte fuse high byte fuse low byte lock bits 9a. enter signature byte read 0100011_00001000 xxxxxxx_xxxxxxxx 9b. load address byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx 9c. read signature byte 0110010_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_oooooooo 10a. enter calibration byte read 0100011_00001000 xxxxxxx_xxxxxxxx 10b. load address byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx 10c. read calibration byte 0110110_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_oooooooo 11a. load no operation command 0100011_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx table 27-18. jtag programming instruction (continued) set a = address high bits, b = address low bits, c = address extended bits, h = 0 - low byte, 1 - high byte, o = data out, i = data in, x = don?t care instruction tdi sequence tdo sequence notes notes: 1. this command sequence is not required if the seven msb are correctly set by the previous command sequence (which is normally the case). 2. repeat until o = ?1?. 3. set bits to ?0? to program the corre sponding fuse, ?1? to unprogram the fuse. 4. set bits to ?0? to program the corresponding lock bit, ?1? to leave the lock bit unchanged. 5. ?0? = programmed, ?1? = unprogrammed. 6. the bit mapping for fuses extended byte is listed in table 27-3 on page 256 7. the bit mapping for fuses high byte is listed in table 27-4 on page 257 8. the bit mapping for fuses low byte is listed in table 27-5 on page 257 9. the bit mapping for lock bits byte is listed in table 27-1 on page 255 10. address bits exceeding pcmsb and eeamsb ( table 27-7 on page 258 and table 27-8 on page 258 ) are don?t care 11. all tdi and tdo sequences are represented by binary digits (0b...). atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 282 figure 27-16. state machine sequence for changing/reading the data word 27.10.11 flash data byte register the flash data byte register provides an efficient way to load the entire flash page buffer befo re executing page write, or to read out/verify the content of the flash. a state machine sets up the control signals to the flash and senses the strobe signal s from the flash, thus only the data words need to be shifted in/out. the flash data byte register actually c onsists of the 8-bit scan chain and a 8-bit temporary register. during page load, the update-dr state copies the content of the scan chain over to the temporary regist er and initiates a write sequence that within 11 tck cycles loads the co ntent of the temporary register in to the flash page buffer. the avr ? automatically alternates between writing the low and the high byte for each new update-dr stat e, starting with the low byte for the first update-dr encountered after entering the prog_pageload command. t he program counter is pre-in cremented before writing the low byte, except for the first written byte. this ensures t hat the first data is writt en to the address set up by prog_commands, and loading the last loca tion in the page buffer does not make th e program counter increment into the next page. during page read, the content of the selected flash byte is capt ured into the flash data byte register during the capture-dr state. the avr automatically alternates between reading the low and the high byte for each new capture-dr st ate, starting with the low byte for the first captur e-dr encountered after entering the prog_pageread command. the program counter is post-incremented after reading each high byte, includ ing the first read byte. this ensures that the first data is captured from the first address set up by prog_commands, an d reading the last location in the page makes the program counter increment into the next page. test logic reset run test/idle select ir scan select dr scan capture ir capture dr 0 00 00 00 shift ir shift dr 11 exit1 ir exit1 dr exit2 ir exit2 dr 00 pause ir pause dr 11 update ir update dr 1 10 10 1 1 00 0 1 1 0 1 0 11 1 1 283 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 figure 27-17. flash data byte register the state machine controlling the flash data byte register is clocked by tck. during normal operation in which eight bits are shifted for each flash byte, the clock cycles needed to naviga te through the tap controller automatically feeds the state machine for the flash data byte register with sufficient number of clock pulses to complete its operation transparently for the user. however, if too few bits are shifted between each update -dr state during page load, the t ap controller should stay in the run-test/idle state for some tck cycles to ensure that there are at least 11 tck cycles between each update-dr state. 27.10.12 programming algorithm all references below of type ?1a?, ?1b?, and so on, refer to table 27-18 on page 279 . 27.10.13 entering programming mode 1. enter jtag instruction avr_reset and shift 1 in the reset register. 2. enter instruction prog_enable and shift 0b1010_0011_0111_0000 in the programming enable register. 27.10.14 leaving programming mode 1. enter jtag instru ction prog_commands. 2. disable all programming instructions by using no operation instruction 11a. 3. enter instruction prog_enable and shift 0b0000_0000_0000_0000 in the programming enable register. 4. enter jtag instruction avr_reset and shift 0 in the reset register. 27.10.15 performing chip erase 1. enter jtag instru ction prog_commands. 2. start chip erase using programming instruction 1a. 3. poll for chip erase complete using prog ramming instruction 1b, or wait for t wlrh_ce (refer to table 27-14 on page 268 ). flash eeprom fuses lock bits d a t a tdi state machine strobes address tdo atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 284 27.10.16 programming the flash before programming the flash a chip erase must be performed, see section 27.10.15 ?performing chip erase? on page 283 . 1. enter jtag instru ction prog_commands. 2. enable flash write using programming instruction 2a. 3. load address extended high byte using programming instruction 2b. 4. load address high byte using programming instruction 2c. 5. load address low byte using programming instruction 2d. 6. load data using programming instructions 2e, 2f and 2g. 7. repeat steps 5 and 6 for all instruction words in the page. 8. write the page using programming instruction 2h. 9. poll for flash write complete using programming instruction 2i, or wait for t wlrh (refer to table 27-14 on page 268 ). 10. repeat steps 3 to 9 until all data have been programmed. a more efficient data transfer can be achi eved using the prog_pageload instruction: 1. enter jtag instru ction prog_commands. 2. enable flash write using programming instruction 2a. 3. load the page address using programming instructions 2b, 2c and 2d. pcword (refer to table 27-7 on page 258 ) is used to address within one page and must be written as 0. 4. enter jtag instru ction prog_pageload. 5. load the entire page by shifting in all instruction words in the page byte-by-byte, starting with the lsb of the first instruction in the page and ending with the msb of the last instruction in the page. use update-dr to copy the contents of the flash data byte regist er into the flash page location and to auto-increment the program counter before each new word. 6. enter jtag instru ction prog_commands. 7. write the page using programming instruction 2h. 8. poll for flash write complete using programming instruction 2i, or wait for t wlrh (refer to table 27-14 on page 268 ). 9. repeat steps 3 to 8 until all data have been programmed. 27.10.17 reading the flash 1. enter jtag instru ction prog_commands. 2. enable flash read using pr ogramming instruction 3a. 3. load address using programming instructions 3b, 3c and 3d. 4. read data using programming instruction 3e. 5. repeat steps 3 and 4 until all data have been read. a more efficient data transfer can be achieved using the prog_pageread instruction: 1. enter jtag instru ction prog_commands. 2. enable flash read using pr ogramming instruction 3a. 3. load the page address using programming instructions 3b, 3c and 3d. pcword (refer to table 27-7 on page 258 ) is used to address within one page and must be written as 0. 4. enter jtag instru ction prog_pageread. 5. read the entire page (or flash) by shifting out all instruct ion words in the page (or flash), starting with the lsb of the first instruction in the page (flash) and ending with t he msb of the last instructio n in the page (flash). the capture-dr state both captur es the data from the flash, and also au to-increments the program counter after each word is read. note that capt ure-dr comes before the shift-dr state. hence, the first byte which is shifted out con- tains valid data. 6. enter jtag instru ction prog_commands. 7. repeat steps 3 to 6 until all data have been read. 285 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 27.10.18 progra mming the eeprom before programming the eeprom a ch ip erase must be performed, see section 27.10.15 ?performing chip erase? on page 283 . 1. enter jtag instru ction prog_commands. 2. enable eeprom write using programming instruction 4a. 3. load address high byte using programming instruction 4b. 4. load address low byte using programming instruction 4c. 5. load data using programming instructions 4d and 4e. 6. repeat steps 4 and 5 for all data bytes in the page. 7. write the data using programming instruction 4f. 8. poll for eeprom write comp lete using programming instruction 4g, or wait for t wlrh (refer to table 27-14 on page 268 ). 9. repeat steps 3 to 8 until all data have been programmed. note that the prog_pageload instruction can not be used when programming the eeprom. 27.10.19 reading the eeprom 1. enter jtag instru ction prog_commands. 2. enable eeprom read using programming instruction 5a. 3. load address using programming instructions 5b and 5c. 4. read data using programming instruction 5d. 5. repeat steps 3 and 4 until all data have been read. note that the prog_pageread instruction can not be used when reading the eeprom. 27.10.20 programming the fuses 1. enter jtag instru ction prog_commands. 2. enable fuse write using programming instruction 6a. 3. load data high byte using programming instructions 6b. a bit value of ?0? will program the corresponding fuse, a ?1? will unprogram the fuse. 4. write fuse high byte using programming instruction 6c. 5. poll for fuse write complete using programming instruction 6d, or wait for t wlrh (refer to table 27-14 on page 268 ). 6. load data low byte using programming instructions 6e. a ?0? will program the fuse, a ?1? will unprogram the fuse. 7. write fuse low byte using programming instruction 6f. 8. poll for fuse write complete using programming instruction 6g, or wait for t wlrh (refer to table 27-14 on page 268 ). 27.10.21 programming the lock bits 1. enter jtag instru ction prog_commands. 2. enable lock bit write using programming instruction 7a. 3. load data using programming instructions 7b. a bit value of ?0? will program the corresponding lock bit, a ?1? will leave the lock bit unchanged. 4. write lock bits using programming instruction 7c. 5. poll for lock bit write comp lete using programming instruction 7d, or wait for t wlrh (refer to table 27-14 on page 268 ). atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 286 27.10.22 reading the fuses and lock bits 1. enter jtag instru ction prog_commands. 2. enable fuse/lock bit read using programming instruction 8a. 3. to read all fuses and lock bits, use programming instruction 8e. to only read fuse high byte, use programming instruction 8b. to only read fuse low byte, use programming instruction 8c. to only read lock bits, use programming instruction 8d. 27.10.23 reading the signature bytes 1. enter jtag instru ction prog_commands. 2. enable signature byte read using programming instruction 9a. 3. load address 0x00 using programming instruction 9b. 4. read first signature byte using programming instruction 9c. 5. repeat steps 3 and 4 with address 0x01 and address 0x02 to read the second and third signature bytes, respectively. 27.10.24 reading the calibration byte 1. enter jtag instru ction prog_commands. 2. enable calibration byte read us ing programming instruction 10a. 3. load address 0x00 using programming instruction 10b. 4. read the calibration byte using programming instruction 10c. 287 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 28. electrical characteristics 28.1 absolute maximum ratings* 28.2 dc characteristics stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond t hose indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability . parameters min. typ. max. unit operating temperature ?55 +125 c storage temperature ?65 +150 c voltage on any pin except reset with respect to ground to ?0.5 v cc + 0.5 v voltage on reset with respect to ground ?0.5 +13.0 v maximum operating voltage 6.0 v dc current per i/o pin 40.0 ma dc current v cc and gnd pins 200.0 ma injection current at v cc = 0v 5.0 (1) ma injection current at v cc = 5v 1.0 ma note: 1. maximum current per port = 30ma table 28-1. t a = ?40c to 125c, v cc = 2.7v to 5.5v (unless otherwise noted) parameters condition symbol min. typ. max. unit input low voltage, except xtal1 and reset pin v cc = 2.7v ? 5.5v v il ?0.5 0.3v cc (1) v input low voltage, xtal1 pin v cc = 2.7v ? 5.5v v il1 ?0.5 0.1v cc (1) v input low voltage, reset pin v cc = 2.7v ? 5.5v v il2 ?0.5 0.2v cc (1) v input high voltage, except xtal1 and reset pins v cc = 2.7v ? 5.5v v ih 0.6v cc (2) v cc + 0.5 v input high voltage, xtal1 pin v cc = 2.7v ? 5.5v v ih1 0.7v cc (2) v cc + 0.5 v input high voltage, reset pin v cc = 2.7v ? 5.5v v ih2 0.9v cc (2) v cc + 0.5 v notes: 1. ?max? means the highest value where the pin is guaranteed to be read as low 2. ?min? means the lowest value where t he pin is guaranteed to be read as high 3. although each i/o port can sink more than the test conditions (20ma at v cc = 5v, 10ma at v cc = 3v) under steady state conditions (non-transient), the following must be observed: 1.) the sum of all iol, for ports pb0-pb7, xtal2, pd0-pd7 should not exceed 100ma. 2.) the sum of all iol, for ports pa0-pa3, pc0-pc7 should not exceed 100ma. if iol exceeds the test condition, vol may exceed the relate d specification. pins are no t guaranteed to sink current greater than the listed test condition. 4. although each i/o port can source more than the test conditions (20ma at v cc = 5v, 10ma at v cc = 3v) under steady state conditions (non-transient), the following must be observed: 1.) the sum of all ioh, for ports pb0-pb7, xtal2, pd0-pd7 should not exceed 100ma. 2.) the sum of all ioh, for ports pa0- pa3, pc0-pc7 should not exceed 100ma. if ioh exceeds the test condition, voh ma y exceed the related specification. pins are not guaranteed to source current greater than the listed test condition. atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 288 output low voltage (3) i ol = 20ma, v cc = 5v i ol = 10ma, v cc = 3v v ol 0.8 0.5 v output high voltage (4) i oh = ?20ma, v cc = 5v i oh = ?10ma, v cc = 3v v oh 4.1 2.3 v input leakage current i/o pin v cc = 5.5v, pin low (absolute value) i il 1 a input leakage current i/o pin v cc = 5.5v, pin high (absolute value) i ih 1 a reset pull-up resistor r rst 30 60 k i/o pin pull-up resistor r pu 20 50 k analog comparator input offset voltage v cc = 5v, 0.1v cc < v in < v cc ? 100mv v acio <10 40 mv analog comparator input leakage current v cc = 5v v in = v cc /2 i aclk ?50 50 na analog comparator propagation delay v cc = 2.7v v cc = 4.0v t acid 750 500 ns table 28-1. t a = ?40c to 125c, v cc = 2.7v to 5.5v (unless othe rwise noted) (continued) parameters condition symbol min. typ. max. unit notes: 1. ?max? means the highest value where the pin is guaranteed to be read as low 2. ?min? means the lowest value where t he pin is guaranteed to be read as high 3. although each i/o port can sink more than the test conditions (20ma at v cc = 5v, 10ma at v cc = 3v) under steady state conditions (non-transient), the following must be observed: 1.) the sum of all iol, for ports pb0-pb7, xtal2, pd0-pd7 should not exceed 100ma. 2.) the sum of all iol, for ports pa0-pa3, pc0-pc7 should not exceed 100ma. if iol exceeds the test condition, vol may exceed the relate d specification. pins are no t guaranteed to sink current greater than the listed test condition. 4. although each i/o port can source more than the test conditions (20ma at v cc = 5v, 10ma at v cc = 3v) under steady state conditions (non-transient), the following must be observed: 1.) the sum of all ioh, for ports pb0-pb7, xtal2, pd0-pd7 should not exceed 100ma. 2.) the sum of all ioh, for ports pa0- pa3, pc0-pc7 should not exceed 100ma. if ioh exceeds the test condition, voh ma y exceed the related specification. pins are not guaranteed to source current greater than the listed test condition. 289 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 28.3 speed grades maximum frequency is depending on v cc. as shown in figure 28-1 , the maximum frequency versus v cc curve is linear between 2.7v < v cc < 4.5v. figure 28-1. maximum frequency versus v cc , atmega164p-b/324p-b/644p-b table 28-2. t a = ?40c to 125c, v cc = 2.7v to 5.5v (unless otherwise noted) parameter condition symbol min. typ. (2) max. unit power supply current (1) active 4mhz, v cc = 3v i cc 1.4 2.75 ma active 8mhz, v cc = 5v 4.8 10 ma active 16mhz, v cc = 5v 8.6 15 ma idle 4mhz, v cc = 3v 0.25 1.5 ma idle 8mhz, v cc = 5v 1.0 3.0 ma idle 16mhz, v cc = 5v 1.9 4.0 ma power-save mode (3) 32khz tosc enabled, v cc = 3v 0.6 a power-down mode (3) wdt enabled, v cc = 3v 4.8 60 a wdt enabled, v cc = 5v 7.3 95 a wdt disabled, v cc = 3v 0.3 54 a wdt disabled, v cc = 5v 0.6 85 a notes: 1. all bits set in the section 10.12.3 ?prr0 ? power redu ction register 0? on page 39 . 2. typical values at 25c. maximum values are test limits in production. 3. the current consumption values include input leakage current. 16mhz 8mhz 2.7v 4.5v 5.5v safe operating area atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 290 28.4 clock characteristics 28.4.1 external clock drive waveforms figure 28-2. external clock drive waveforms 28.4.2 external clock drive table 28-3. calibration accuracy of internal rc oscillator frequency v cc temperature calibration accuracy default 3v factory calibration 8.0mhz 3v 25c 1.5% 8.0mhz 2.7 - 5.5v (1) ?40c / +125c 14% 5v factory calibration 8.0mhz 5v 25c 1.5% 8.0mhz 4.5 - 5.5v (1) ?40c / +125c 10% watchdog oscillator 128khz 2.7 - 5.5v (1) ?40c / +125c 40% note: 1. voltage range for atmel ? atmega164p-b/324p-b/644p-b. t chcx v ih1 v il1 t chcx t clch t chcl t clcx t clcl table 28-4. external clock drive parameter symbol v cc = 2.7 to 5.5v v cc = 4.5 to 5.5v unit min. max. min. max. oscillator frequency 1/t clcl 0 8 0 16 mhz clock period t clcl 125 62.5 ns high time t chcx 40 20 ns low time t clcx 40 20 ns rise time t clch 1.6 0.5 s fall time t chcl 1.6 0.5 s change in period from one clock cycle to the next t clcl 2 2 % 291 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 28.5 system and reset characteristics 28.6 external interrupts characteristics table 28-5. reset, brown-out and internal voltage reference characteristics parameter condition symbol min typ. max unit power-on reset threshold voltage (rising) v pot 1.1 1.4 1.6 v power-on reset threshold voltage (falling) (1) 0.6 1.3 1.6 v reset pin threshold voltage v rst 0.2v cc 0.9v cc v minimum pulse width on reset pin t rst 2.5 s brown-out detector hysteresis v hyst 80 mv min pulse width on brown-out reset t bod 2 s bandgap reference voltage v cc = 2.7v, t a = 25c v bg 0.98 1.1 1.22 v bandgap reference start-up time v cc = 2.7v, t a = 25c t bg 40 70 s note: 1. the power-on reset will not work unless the supply voltage has been below v pot (falling). table 28-6. bodlevel fuse coding (1) bodlevel 2:0 fuses min v bot typical v bot max v bot unit 111 bod disabled 110 1.7 1.8 2.0 v 101 2.5 2.7 2.9 100 4.0 4.3 4.55 011 reserved 010 001 000 note: 1. v bot may be below nominal minimum operating voltage for some devices. for devices where this is the case, the device is tested down to v cc = v bot during the production test. this gua rantees that a br own-out reset will occur before v cc drops to a voltage where correct operation of the microcontroller is no longer guaranteed. the test is performed using bodlevel = 101 and bodlevel = 110. table 28-7. asynchronous external interrupt characteristics parameter condition symbol min typ. max unit minimum pulse width for asynchronous external interrupt t int 50 ns atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 292 28.7 spi timing characteristics see figure 28-3 and figure 28-4 on page 293 for details. figure 28-3. spi interface timing requirements (master mode) table 28-8. spi timing parameters description mode min typ. max 1 sck period master see table 18-5 on page 145 ns 2 sck high/low master 50% duty cycle 3 rise/fall time master 3.6 4 setup master 10 5 hold master 10 6 out to sck master 0.5 t sck 7 sck to out master 10 8 sck to out high master 10 9 ss low to out slave 15 10 sck period slave 4 t ck 11 sck high/low (1) slave 2 t ck 12 rise/fall time slave 1600 13 setup slave 10 14 hold slave t ck 15 sck to out slave 15 16 sck to ss high slave 20 17 ss high to tri-state slave 10 18 ss low to sck slave 20 note: 1. in spi programming mode the minimum sck high/low period is: ? 2 t clcl for f ck < 12mhz ?3 t clcl for f ck > 12mhz 6 msb ss sck (cpol = 0) sck (cpol = 1) miso (data input) mosi (data output) msb lsb lsb ... ... 45 8 7 1 2 2 3 293 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 figure 28-4. spi interface timi ng requirements (slave mode) 28.8 2-wire serial interface characteristics table 28-9 describes the requirements for devices conn ected to the 2-wire serial bus. the atmel ? atmega164p-b/324p-b/644p-b 2-wire serial interface meets or exceeds these requirement s under the noted conditions. timing symbols refer to figure 28-5 on page 294 . 9 msb ss sck (cpol = 0) sck (cpol = 1) mosi (data input) miso (data output) msb lsb x lsb ... ... 13 14 17 15 10 16 11 11 12 table 28-9. 2-wire serial bus requirements parameter condition symbol min max unit input low-voltage v il ?0.5 0.3 v cc v input high-voltage v ih 0.7 v cc v cc + 0.5 v hysteresis of schmitt trigger inputs v hys (1) 0.05 v cc (2) ? v output low-voltage 3ma sink current v ol (1) 0 0.4 v rise time for both sda and scl t r (1) 20 + 0.1c b (2)(3) 300 ns output fall time from v ihmin to v ilmax 10pf < c b < 400pf (3) t of (1) 20 + 0.1c b (2)(3) 250 ns spikes suppressed by input filter t sp (1) 0 50 (2) ns input current each i/o pin 0.1v cc < v i < 0.9v cc i i ?10 10 a capacitance for each i/o pin c i (1) ? 10 pf scl clock frequency f ck (4) > max(16f scl , 250khz) (5) f scl 0 400 khz notes: 1. in atmega164p-b/324p-b/644p-b, this pa rameter is characterized and not 100% tested. 2. required only for f scl > 100khz. 3. cb = capacitance of one bus line in pf. 4. f ck = cpu clock frequency 5. this requirement applies to all atm ega164p-b/324p-b/644p-b two-wire serial interface operation. other devices con- nected to the two-wire serial bus need only obey the general f scl requirement. 6. the actual low period generated by the atmega164p- b/324p-b/644p-b two-wire serial interface is (1/f scl ? 2/f ck ), thus f ck must be greater than 6mhz for the low ti me requirement to be strictly met at f scl = 100khz. 7. the actual low period generated by the atmega1 64p-b/324p-b/644p-b two-wire serial interface is (1/f scl ?2/f ck ), thus the low time requirement will not be strictly met for f scl > 308khz when f ck = 8mhz. still, atmega164p-b/324p-b/644p-b devices connected to the bu s may communicate at full speed (400khz) with other atmega164p-b/324p-b/644p-b devices, as we ll as any other device with a proper t low acceptance margin. atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 294 figure 28-5. 2-wire serial bus timing value of pull-up resistor f scl 100khz rp f scl > 100khz rp hold time (repeated) start condition f scl 100khz t hd;sta 4.0 ? s f scl > 100khz 0.6 ? s low period of the scl clock f scl 100khz (6) t low 4.7 ? s f scl > 100khz (7) 1.3 ? s high period of the scl clock f scl 100khz t high 4.0 ? s f scl > 100khz 0.6 ? s set-up time for a repeated start condition f scl 100khz t su;sta 4.7 ? s f scl > 100khz 0.6 ? s data hold time f scl 100khz t hd;dat 0 3.45 s f scl > 100khz 0 0.9 s data setup time f scl 100khz t su;dat 250 ? ns f scl > 100khz 100 ? ns setup time for stop condition f scl 100khz t su;sto 4.0 ? s f scl > 100khz 0.6 ? s bus free time between a stop and start condition f scl 100khz t buf 4.7 ? s f scl > 100khz 1.3 ? s table 28-9. 2-wire serial bus requirements (continued) parameter condition symbol min max unit notes: 1. in atmega164p-b/324p-b/644p-b, this pa rameter is characterized and not 100% tested. 2. required only for f scl > 100khz. 3. cb = capacitance of one bus line in pf. 4. f ck = cpu clock frequency 5. this requirement applies to all atm ega164p-b/324p-b/644p-b two-wire serial interface operation. other devices con- nected to the two-wire serial bus need only obey the general f scl requirement. 6. the actual low period generated by the atmega164p- b/324p-b/644p-b two-wire serial interface is (1/f scl ? 2/f ck ), thus f ck must be greater than 6mhz for the low ti me requirement to be strictly met at f scl = 100khz. 7. the actual low period generated by the atmega1 64p-b/324p-b/644p-b two-wire serial interface is (1/f scl ?2/f ck ), thus the low time requirement will not be strictly met for f scl > 308khz when f ck = 8mhz. still, atmega164p-b/324p-b/644p-b devices connected to the bu s may communicate at full speed (400khz) with other atmega164p-b/324p-b/644p-b devices, as we ll as any other device with a proper t low acceptance margin. v cc 0,4v ? 3ma --------------------------- - 1000ns c b ---------------- - v cc 0,4v ? 3ma --------------------------- - 300ns c b ------------- - t of t su,sta t hd,sta t hd,sta t buf t hd,dat t su,dat t high t low t low scl sda t r 295 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 28.9 adc characteristics table 28-10. adc characteristi cs, single ended channel parameter condition symbol min typ. max unit resolution single ended conversion 10 bit absolute accuracy v cc = 4v, v ref = 4v, adc clock = 200khz tue 2.5 4 lsb v cc = 4v, v ref = 4v, adc clock = 200khz, noise reduction mode on. tue 2.5 4 lsb integral non linearity v cc = 4v, v ref = 4v, adc clock = 200khz inl 0.5 1.5 lsb differential non linearity v cc = 4v, v ref = 4v, adc clock = 200khz dnl 0.3 0.7 lsb gain error v cc = 4v, v ref = 4v, adc clock = 200khz ?4 ?2 4 lsb offset error v cc = 4v, v ref = 4v, adc clock = 200khz 4 2 4 lsb conversion time free running conversion 65 260 s clock frequency single ended conversion 50 200 khz analog supply voltage avcc v cc ? 0.3 v cc + 0.3 v reference voltage v ref 1.00 avcc v input voltage v in gnd v ref v internal voltage reference 1.1v v int1 0.96 1.1 1.2 v internal voltage reference 2.56v, v cc > 2.7v v int2 2.33 2.56 2.79 v reference input resistance r ref 30 40% k analog input resistance r ain 100 m atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 296 table 28-11. adc characterist ics, differential channels parameter condition symbol min typ. max unit resolution gain = 1x 8 bit gain = 10x 8 gain = 200x 7 absolute accuracy (including inl, dnl quantization error and offset error) gain = 1x v cc = 5v, v ref = 4v adc clock = 200khz tue 4.6 7 lsb gain = 10x v cc = 5v, v ref = 4v adc clock = 200khz 4.8 8 gain = 200x v cc = 5v, v ref = 4v adc clock = 200khz 1.0 4 integral non-linearity (inl) gain = 1x v cc = 5v, v ref = 4v adc clock = 200khz inl 0.3 1.5 gain = 10x v cc = 5v, v ref = 4v adc clock = 200khz 0.3 1.5 gain = 200x v cc = 5v, v ref = 4v adc clock = 200khz 0.3 1.5 differential non-linearity (dnl) gain = 1x v cc = 5v, v ref = 4v adc clock = 200khz dnl 0.2 1.0 gain = 10x v cc = 5v, v ref = 4v adc clock = 200khz 0.2 1.0 gain = 200x v cc = 5v, v ref = 4v adc clock = 200khz 0.3 1.0 gain error gain = 1x v cc = 5v, v ref = 4v adc clock = 200khz ?12 ?9 ?4 lsb gain = 10x v cc = 5v, v ref = 4v adc clock = 200khz ?12 ?9 ?4 gain = 200x v cc = 5v, v ref = 4v adc clock = 200khz ?3 ?1 3 offset error gain = 1x v cc = 5v, v ref = 4v adc clock = 200khz ?4 0.3 4 gain = 10x v cc = 5v, v ref = 4v adc clock = 200khz ?4 0.2 4 gain = 200x v cc = 5v, v ref = 4v adc clock = 200khz ?4 -0.5 3 reference voltage v ref 2.56 avcc ? 0.5 v 297 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 29. typical characteristics the following charts show typical behavior. these figures ar e not tested during manufactur ing. all current consumption measurements are performed with all i/o pi ns configured as inputs and with internal pull-ups enabled. a sine wave generator with rail-to-rail output is used as clock source. all active- and idle current consumption measurements are done with all bits in the prr registers set and thus, the corresponding i/o modules are turned off. also the analog co mparator is disabled during these measurements. the power consumption in power-down mode is independent of clock selection. the current consumption is a function of several factors such as: operating voltage, operating fr equency, loading of i/o pins, switching rate of i/o pins, code exec uted and ambient temperature. the dominat ing factors are operating voltage and frequency. the current drawn from capacitive loaded pins may be estimated (for one pin) as c l v cc f where c l = load capacitance, v cc = operating voltage and f = average switching frequency of i/o pin. the parts are characterized at frequencies higher than test limits. parts are no t guaranteed to function properly at frequencies higher than the ordering code indicates. the difference between current consumption in power-down mode with watchdog timer enabled and power-down mode with watchdog timer disabled represents the differential current drawn by the watchdog timer. 29.1 atmega164p-b typical characteristics 29.1.1 active supply current figure 29-1. atmega164p-b: active supply current versus low frequency (0.1 - 1.0mhz) figure 29-2. atmega164p-b: active supply current versus frequency (1 - 16mhz) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 frequency (mhz) 1.4 1.2 1.0 1.6 0.8 0.6 0.4 0.2 0 i cc (ma) 6.0 5.5 5.0 4.5 4.0 3.6 3.3 3.0 2.7 2.4 2.2 2.0 1.8 0 2 4 6 8 10 12 14 16 frequency (mhz) 14 12 10 16 18 8 6 4 2 0 i cc (ma) 6.0 5.5 5.0 4.5 4.0 3.6 3.3 3.0 2.7 2.4 2.2 2.0 1.8 atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 298 29.1.2 idle supply current figure 29-3. atmega164p-b: idle supply current versus low frequency (0.1 - 1.0mhz) figure 29-4. atmega164p-b: idle supply current versus frequency (1 - 16mhz) 29.1.3 power-down supply current figure 29-5. atmega164p-b: power-down supply current versus v cc (watchdog timer disabled) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 frequency (mhz) 0.3 0.25 0.2 0.15 0.1 0.05 0 i cc (ma) 6.0 5.5 5.0 4.5 4.0 3.6 3.3 3.0 2.7 2.4 2.2 2.0 1.8 0 2 4 6 8 10 12 14 16 frequency (mhz) 3 2.5 4 3.5 2 1.5 1 0.5 0 i cc (ma) 6.0 5.5 5.0 4.5 4.0 3.6 3.3 3.0 2.7 2.4 2.2 2.0 1.8 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3 v cc (v) 120 100 80 60 40 20 0 i cc (a) 150 125 85 25 -40 299 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 figure 29-6. atmega164p-b: power-down supply current versus v cc (watchdog timer enabled) 29.1.4 pin pull-up figure 29-7. atmega164p-b: i/o pin pull-up resistor current versus input voltage (v cc = 5v) figure 29-8. atmega164p-b: reset pull-up resistor current versus reset pin voltage (v cc =5v) 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3 v cc (v) 120 100 80 60 40 20 0 i cc (a) 150 125 85 25 -40 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 v op (v) 120 100 160 140 80 60 40 20 0 i op (a) 150 125 85 25 -40 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 v reset (v) 120 100 80 60 40 20 0 i reset (a) 150 125 85 25 -40 atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 300 29.1.5 pin driver strength figure 29-9. atmega164p-b: i/o pin output voltage versus sink current (v cc = 3v) figure 29-10. atmega164p-b: i/o pin output voltage versus sink current (v cc = 5v) figure 29-11. atmega164p-b: i/o pin output voltage versus source current (v cc = 3v) 1 3 5 7 9 11 13 15 17 19 load current (ma) 1.2 1.4 1 0.8 0.6 0.4 0.2 0 v ol (v) 150 125 85 25 -40 1 3 5 7 9 11 13 15 17 19 load current (ma) 0.6 0.7 0.5 0.9 1 0.8 0.4 0.3 0.2 0.1 0 v ol (v) 150 125 85 25 -40 0 2 4 6 8 10 12 14 16 18 20 load current (ma) 3 3.5 2.5 2 1.5 1 0.5 0 v oh (v) 150 125 85 25 -40 301 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 figure 29-12. atmega164p-b: i/o pin output voltage versus source current (v cc = 5v) 29.1.6 pin threshold figure 29-13. atmega164p-b: i/o pin input threshold versus v cc (v ih , i/o pin read as ?1?) figure 29-14. atmega164p-b: i/o pin input threshold versus v cc (v il , i/o pin read as ?0?) 0 2 4 6 8 101214 1618 20 load current (ma) 5.2 5 4.8 4.6 4.4 4.2 4 v oh (v) 150 125 85 25 -40 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3 v cc (v) 3 2.5 4 3.5 2 1.5 1 0.5 0 threshold (v) 150 125 85 25 -40 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3 v cc (v) 3 2.5 2 1.5 1 0.5 0 threshold (v) 150 125 85 25 -40 atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 302 figure 29-15. atmega164p-b: reset pin input threshold versus v cc (v ih , i/o pin read as ?1?) figure 29-16. atmega164p-b: reset pin input threshold versus v cc (v il , i/o pin read as ?0?) 29.1.7 bod threshold figure 29-17. atmega164p-b: bod threshold versus temperature (v bot = 4.3v) 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3 v cc (v) 3 2.5 2 1.5 5 4.5 4 3.5 1 0.5 0 threshold (v) 150 125 85 25 -40 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3 v cc (v) 2.5 2 1.5 1 0.5 0 threshold (v) 150 125 85 25 -40 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 temperature (c) 4.5 4.6 4.4 4.3 4.2 4.1 4 threshold (v) 1 0 303 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 figure 29-18. atmega164p-b: bod threshold versus temperature (v bot = 2.7v) figure 29-19. atmega164p-b: calibrated bandgap voltage versus v cc figure 29-20. atmega164p-b: bandgap voltage versus temperature -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 temperature (c) 2.75 2.8 2.85 2.9 2.7 2.65 2.6 2.55 2.5 threshold (v) 1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) 1.12 1.10 1.08 1.06 1.2 1.18 1.16 1.14 1.04 1.02 1 bandgap voltage (v) 150 125 85 25 -40 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 temperature (c) 1.1 1.12 1.14 1.16 1.18 1.2 1.08 1.06 1.04 1.02 1 bandgap voltage (v) 5.5 5.0 4.5 3.6 3.0 2.7 1.8 atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 304 29.1.8 internal oscillator speed figure 29-21. atmega164p-b: watchdog oscillator frequency versus temperature figure 29-22. atmega164p-b: watchdog oscillator frequency versus v cc figure 29-23. atmega164p-b: calibrate d 8mhz rc oscillator versus v cc -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 temperature (c) 140 135 130 125 120 115 f rc (khz) 6.0 5.5 5.0 4.5 4.0 3.6 3.3 3.0 2.7 1.8 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) 140 135 130 125 120 115 f rc (khz) 150 125 85 25 -40 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) 7.9 7.85 7.8 7.75 7.7 8.15 8.1 8.05 8 7.95 7.65 f rc (mhz) 150 125 85 25 -40 305 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 figure 29-24. atmega164p-b: calibrated 8m hz rc oscillator versus temperature figure 29-25. atmega164p-b: calibrated 8mhz rc oscillator versus osccal value 29.2 atmega324p-b typical characteristics 29.2.1 active supply current figure 29-26. atmega324p-b: active supply cu rrent versus low frequency (0.1 - 1.0mhz) -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 temperature (c) 7.9 7.95 8 8.05 8.1 8.15 7.85 7.8 7.75 7.7 7.65 f rc (mhz) 5.5 5.0 4.5 4.0 3.6 3.0 2.7 1.8 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 osccal (x1) 10 8 6 4 2 18 16 12 14 0 f rc (mhz) 150 125 85 25 -40 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 frequency (mhz) 1.4 1.2 1 1.6 0.8 0.6 0.4 0.2 0 i cc (ma) 6.0 5.5 5.0 4.5 4.0 3.6 3.3 3.0 2.7 2.4 2.2 2.0 1.8 atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 306 figure 29-27. atmega324p-b: active supply current versus frequency (1 - 16mhz) 29.2.2 idle supply current figure 29-28. atmega324p-b: idle supply current versus low frequency (0.1 - 1.0mhz) figure 29-29. atmega324p-b: idle supply current versus frequency (1 - 16mhz) 0246810121416 frequency (mhz) 14 12 10 16 18 8 6 4 2 0 i cc (ma) 6.0 5.5 5.0 4.5 4.0 3.6 3.3 3.0 2.7 2.4 2.2 2.0 1.8 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 frequency (mhz) 0.3 0.35 0.25 0.2 0.15 0.1 0.05 0 i cc (ma) 6.0 5.5 5.0 4.5 4.0 3.6 3.3 3.0 2.7 2.4 2.2 2.0 1.8 1.6 0 2 4 6 8 10 12 14 16 frequency (mhz) 3 3.5 4 2.5 2 1.5 1 0.5 0 i cc (ma) 6.0 5.5 5.0 4.5 4.0 3.6 3.3 3.3 2.7 2.4 2.2 2.0 1.8 307 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 29.2.3 power-down supply current figure 29-30. atmega324p-b: power-down supply current versus v cc (watchdog timer disabled) figure 29-31. atmega324p-b: power-down supply current versus v cc (watchdog timer enabled) 29.2.4 pin pull-up figure 29-32. atmega324p-b: i/o pin pull-up resistor current versus input voltage (v cc = 5v) 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3 v cc (v) 120 100 80 60 40 20 0 i cc (a) 150 125 85 25 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3 v cc (v) 120 100 80 60 40 20 0 i cc (a) 150 125 85 25 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 v op (v) 120 100 160 140 80 60 40 20 0 i op (a) 150 125 85 25 -40 atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 308 figure 29-33. atmega324p-b: reset pull-up resistor current versus reset pin voltage (v cc =5v) 29.2.5 pin driver strength figure 29-34. atmega324p-b: i/o pin output voltage versus sink current (v cc = 3v) figure 29-35. atmega324p-b: i/o pin output voltage versus sink current (v cc = 5v) 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 v reset (v) 120 100 80 60 40 20 0 i reset (a) 150 125 85 25 -40 1 3 5 7 9 11 13 15 17 19 load current (ma) 1.2 1.4 1 0.8 0.6 0.4 0.2 0 v ol (v) 150 125 85 25 -40 1 3 5 7 9 11 13 15 17 19 load current (ma) 1.2 1.4 1 0.8 0.6 0.4 0.2 0 v ol (v) 150 125 85 25 -40 309 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 figure 29-36. atmega324p-b: i/o pin output voltage versus source current (v cc = 3v) figure 29-37. atmega324p-b: i/o pin output voltage versus source current (v cc = 5v) 29.2.6 pin threshold figure 29-38. atmega324p-b: i/o pin input threshold versus v cc (v ih , i/o pin read as ?1?) 0 2 4 6 8 101214161820 load current (ma) 3 3.5 2.5 2 1.5 1 0.5 0 v oh (v) 150 125 85 25 -40 0 2 4 6 8 101214161820 load current (ma) 5.2 5 4.8 4.6 4.4 4.2 4 v oh (v) 150 125 85 25 -40 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3 v cc (v) 3 2.5 4 3.5 2 1.5 1 0.5 0 threshold (v) 150 125 85 25 -40 atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 310 figure 29-39. atmega324p-b: i/o pin input threshold versus v cc (v il , i/o pin read as ?0?) figure 29-40. atmega324p-b: reset pin input threshold versus v cc (v ih , i/o pin read as ?1?) figure 29-41. atmega324p-b: reset pin input threshold versus v cc (v il , i/o pin read as ?0?) 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3 v cc (v) 3 2.5 2 1.5 1 0.5 0 threshold (v) 150 125 85 25 -40 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3 v cc (v) 3 2.5 4 3.5 5 4.5 2 1.5 1 0.5 0 threshold (v) 150 125 85 25 -40 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3 v cc (v) 2.5 2 1.5 1 0.5 0 threshold (v) 150 125 85 25 -40 311 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 29.2.7 bod threshold figure 29-42. atmega324p-b: bod threshold versus temperature (v bot = 4.3v) figure 29-43. atmega324p-b: bod threshold versus temperature (v bot = 2.7v) figure 29-44. atmega324p-b: calibrated bandgap voltage versus v cc -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 temperature (c) 4.5 4.6 4.4 4.3 4.2 4.1 4 threshold (v) 1 0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 temperature (c) 2.75 2.8 2.85 2.9 2.7 2.65 2.6 2.55 2.5 threshold (v) 1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) 1.12 1.10 1.08 1.06 1.2 1.18 1.16 1.14 1.04 1.02 1 bandgap voltage (v) 150 125 85 25 -40 atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 312 figure 29-45. atmega324p-b: bandgap voltage versus temperature 29.2.8 internal oscillator speed figure 29-46. atmega324p-b: watchdog oscillator frequency versus temperature figure 29-47. atmega324p-b: watchdog oscillator frequency versus v cc -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 temperature (v) 1.1 1.12 1.14 1.16 1.18 1.2 1.08 1.06 1.04 1.02 1 bandgap voltage (v) 6.0 5.5 5.0 4.5 4.0 3.6 3.3 3.0 2.7 1.8 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 temperature (c) 125 120 115 140 135 130 110 105 100 f rc (khz) 6.0 5.5 5.0 4.5 4.0 3.6 3.3 3.0 2.7 1.8 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) 140 135 130 125 120 115 110 105 100 f rc (khz) 150 125 85 25 -40 313 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 figure 29-48. atmega324p-b: calibrate d 8mhz rc oscillator versus v cc figure 29-49. atmega324p-b: calibrated 8m hz rc oscillator versus temperature figure 29-50. atmega324p-b: calibrated 8mhz rc oscillator versus osccal value 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) 8.4 8.2 8 7.8 7.6 8.6 7.4 f rc (mhz) 150 125 85 25 -40 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 temperature (c) 8.4 8.6 8.2 8 7.8 7.6 7.4 f rc (mhz) 5.5 5.0 4.5 4.0 3.6 3.3 3.0 2.7 1.8 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 osccal (x1) 10 8 6 4 2 16 12 14 0 f rc (mhz) 150 125 85 25 -40 atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 314 29.3 atmega644p-b typical characteristics 29.3.1 active supply current figure 29-51. atmega644p-b: active supply cu rrent versus low frequency (0.1 - 1.0mhz) figure 29-52. atmega644p-b: active supply current versus frequency (1 - 16mhz) 29.3.2 idle supply current figure 29-53. atmega644p-b: idle supply current versus low frequency (0.1 - 1.0mhz) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 frequency (mhz) 1.4 1.2 1 1.6 0.8 0.6 0.4 0.2 0 i cc (ma) 6.0 5.5 5.0 4.5 4.0 3.6 3.3 3.0 2.7 2.4 2.2 2.0 1.8 0246810121416 frequency (mhz) 14 12 10 16 18 8 6 4 2 0 i cc (ma) 6.0 5.5 5.0 4.5 4.0 3.6 3.3 3.0 2.7 2.4 2.2 2.0 1.8 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 frequency (mhz) 0.3 0.35 0.25 0.2 0.15 0.1 0.05 0 i cc (ma) 6.0 5.5 5.0 4.5 4.0 3.6 3.3 3.0 2.7 2.4 2.2 2.0 1.8 315 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 figure 29-54. atmega644p-b: idle supply current versus frequency (1 - 16mhz) 29.3.3 power-down supply current figure 29-55. atmega644p-b: power-down supply current versus v cc (watchdog timer disabled) figure 29-56. atmega644p-b: power-down supply current versus v cc (watchdog timer enabled) 0246810121416 frequency (mhz) 3 2.5 4 3.5 2 1.5 1 0.5 0 i cc (ma) 6.0 5.5 5.0 4.5 4.0 3.6 3.3 3.0 2.7 2.4 2.2 2.0 1.8 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3 v cc (v) 120 100 80 60 40 20 0 i cc (a) 150 125 85 25 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3 v cc (v) 120 140 100 80 60 40 20 0 i cc (a) 150 125 85 25 atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 316 29.3.4 pin pull-up figure 29-57. atmega644p-b: i/o pin pull-up resistor current versus input voltage (v cc = 5v) figure 29-58. atmega644p-b: reset pull-up resistor current versus reset pin voltage (v cc =5v) 29.3.5 pin driver strength figure 29-59. atmega644p-b: i/o pin output voltage versus sink current (v cc = 3v) 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 v op (v) 120 100 160 140 80 60 40 20 0 i op (a) 150 125 85 25 -40 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 v reset (v) 120 100 80 60 40 20 0 i reset (a) 150 125 85 25 -40 1 3 5 7 9 11 13 15 17 19 load current (ma) 1.2 1.4 1 0.8 0.6 0.4 0.2 0 v ol (v) 150 125 85 25 -40 317 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 figure 29-60. atmega644p-b: i/o pin output voltage versus sink current (v cc = 5v) figure 29-61. atmega644p-b: i/o pin output voltage versus source current (v cc = 3v) figure 29-62. atmega644p-b: i/o pin output voltage versus source current (v cc = 5v) 13 57 91113151719 load current (ma) 1.2 1.4 1 0.8 0.6 0.4 0.2 0 v ol (v) 150 125 85 25 -40 0 2 4 6 8 10 12 14 16 18 20 load current (ma) 3 3.5 2.5 2 1.5 1 0.5 0 v oh (v) 150 125 85 25 -40 0 2 4 6 8 10 12 14 16 18 20 load current (ma) 5.2 5 4.8 4.6 4.4 4.2 4 v oh (v) 150 125 85 25 -40 atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 318 29.3.6 pin threshold figure 29-63. atmega644p-b: i/o pin input threshold versus v cc (v ih , i/o pin read as ?1?) figure 29-64. atmega644p-b: i/o pin input threshold versus v cc (v il , i/o pin read as ?0?) figure 29-65. atmega644p-b: reset pin input threshold versus v cc (v ih , i/o pin read as ?1?) 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3 v cc (v) 3 2.5 4 3.5 2 1.5 1 0.5 0 threshold (v) 150 125 85 25 -40 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3 v cc (v) 3 2.5 2 1.5 1 0.5 0 threshold (v) 150 125 85 25 -40 1.82.32.83.33.84.3 4.85.3 v cc (v) 3 2.5 4 3.5 5 4.5 2 1.5 1 0.5 0 threshold (v) 150 125 85 25 -40 319 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 figure 29-66. atmega644p-b: reset pin input threshold versus v cc (v il , i/o pin read as ?0?) 29.3.7 bod threshold figure 29-67. atmega644p-b: bod threshold versus temperature (v bot = 4.3v) figure 29-68. atmega644p-b: bod threshold versus temperature (v bot = 2.7v) 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3 v cc (v) 2.5 2 1.5 1 0.5 0 threshold (v) 150 125 85 25 -40 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 temperature (c) 4.5 4.6 4.4 4.3 4.2 4.1 4 threshold (v) 1 0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 temperature (c) 2.75 2.8 2.85 2.9 2.7 2.65 2.6 2.55 2.5 threshold (v) 1 0 atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 320 figure 29-69. atmega644p-b: calibrated bandgap voltage versus v cc figure 29-70. atmega644p-b: bandgap voltage versus temperature 29.3.8 internal oscillator speed figure 29-71. atmega644p-b: watchdog oscillator frequency versus temperature 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3 v cc (v) 1 1.12 1.1 1.08 1.06 1.2 1.18 1.16 1.14 1.04 1.02 bandgap voltage (v) 150 125 85 25 -40 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 temperature (v) 1.1 1.12 1.14 1.16 1.18 1.2 1.08 1.06 1.04 1.02 1 bandgap voltage (v) 6.0 5.5 5.0 4.5 4.0 3.6 3.3 3.0 2.7 1.8 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 temperature (c) 150 160 140 130 120 110 100 f rc (khz) 6.0 5.5 5.0 4.5 4.0 3.6 3.3 3.0 2.7 1.8 321 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 figure 29-72. atmega644p-b: watchdog oscillator frequency versus v cc figure 29-73. atmega644p-b: calibrate d 8mhz rc oscillator versus v cc figure 29-74. atmega644p-b: calibrated 8m hz rc oscillator versus temperature 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3 v cc (v) 160 150 140 130 120 110 100 f rc (khz) 150 125 85 25 -40 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) 8.4 8.2 8 7.8 7.6 8.6 7.4 f rc (mhz) 150 125 85 25 -40 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 temperature (c) 8.4 8.6 8.2 8 7.8 7.6 7.4 f rc (mhz) 5.5 5.0 4.5 4.0 3.6 3.3 3.0 2.7 1.8 atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 322 figure 29-75. atmega644p-b: calibrated 8mhz rc oscillator versus osccal value 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 osccal (x1) 25 20 15 10 5 0 f rc (mhz) 150 125 85 25 -40 323 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 30. register summary address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page (0xff) reserved - - - - - - - (0xfe) reserved - - - - - - - - (0xfd) reserved - - - - - - - - (0xfc) reserved tccr2b - - - - - - - - (0xfb) reserved - - - - - - - (0xfa) reserved - - - - - - - - (0xf9) reserved - - - - - - - (0xf8) reserved - - - - - - - - (0xf7) reserved - - - - - - - - (0xf6) reserved tccr2b - - - - - - - - (0xf5) reserved - - - - - - - (0xf4) reserved - - - - - - - - (0xf3) reserved - - - - - - - - (0xf2) reserved tccr2b - - - - - - - - (0xf1) reserved - - - - - - - (0xf0) reserved - - - - - - - - (0xef) reserved - - - - - - - (0xee) reserved - - - - - - - - (0xed) reserved - - - - - - - - (0xec) reserved tccr2b - - - - - - - - (0xeb) reserved - - - - - - - (0xea) reserved - - - - - - - - (0xe9) reserved - - - - - - - - (0xe8) reserved tccr2b - - - - - - - - (0xe7) reserved - - - - - - - (0xe6) reserved - - - - - - - - (0xe5) reserved - - - - - - - - (0xe4) reserved tccr2b - - - - - - - - (0xe3) reserved - - - - - - - (0xe2) reserved - - - - - - - - (0xe1) reserved - - - - - - - - (0xe0) reserved - - - - - - - notes: 1. for compatibility with future devices, reserved bits s hould be written to zero if accessed. reserved i/o memory addresses should never be written. 2. i/o registers within the address range $00 - $1f are directly bit-accessible using the sbi and cbi instructions. in these registers, the value of single bits can be checked by using the sbis and sbic instructions. 3. some of the status flags are cleared by writing a logical o ne to them. note that the cbi and sbi instructions will operate on all bits in the i/o register, writing a one back into any flag read as set, thus clearing the flag. the cbi and sbi instructions work with registers 0x00 to 0x1f only. 4. when using the i/o specific commands in and out, t he i/o addresses $00 - $3f must be used. when addressing i/o registers as data space using ld and st instructions, $20 must be added to these addresses. the atmega164p-b/324p-b/644p-b is a complex microcontro ller with more peripheral units than can be supported within the 64 location reserved in opcode for the in and ou t instructions. for the extended i/o space from $60 - $ff, only the st/sts/std and ld/lds/ldd instructions can be used. 5. usart in spi master mode. atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 324 (0xdf) reserved - - - - - - - - (0xde) reserved - - - - - - - - (0xdd) reserved tccr2b - - - - - - - - (0xdc) reserved - - - - - - - (0xdb) reserved - - - - - - - - (0xda) reserved - - - - - - - - (0xd9) reserved - - - - - - - - (0xd8) reserved - - - - - - - - (0xd7) reserved - - - - - - - - (0xd6) reserved - - - - - - - - (0xd5) reserved - - - - - - - - (0xd4) reserved - - - - - - - - (0xd3) reserved - - - - - - - - (0xd2) reserved - - - - - - - - (0xd1) reserved - - - - - - - - (0xd0) reserved - - - - - - - - (0xcf) reserved - - - - - - - - (0xce) udr1 usart1 i/o data register usart0 i/o data register 163 (0xcd) ubrr1h - - - - usart1 baud rate register high byte 166 / 175 (0xcc) ubrr1l usart1 baud rate register low byte 166 / 175 (0xcb) reserved - - - - - - - - (0xca) ucsr1c umsel11 umsel10 upm11 upm10 usbs1 ucsz11/udord0 (5) ucsz10/ucpha0 (5) ucpol1 165 / 175 (0xc9) ucsr1b rxcie1 txcie1 udrie1 rxen1 txen1 ucsz12 rxb81 txb81 164 / 174 (0xc8) ucsr1a rxc1 txc1 udre1 fe1 dor1 upe1 u2x1 mpcm1 163 / 173 (0xc7) reserved - - - - - - - - (0xc6) udr0 usart0 i/o data register usart0 i/o data register 163 (0xc5) ubrr0h - - - - usart0 baud rate register high byte 166 / 175 (0xc4) ubrr0l usart0 baud rate register low byte 166 / 175 (0xc3) reserved - - - - - - - - (0xc2) ucsr0c umsel01 umsel00 upm01 upm00 usbs0 ucsz01/udord0 (5) ucsz00/ucpha0 (5) ucpol0 165 / 175 (0xc1) ucsr0b rxcie0 txcie0 udrie0 rxen0 txen0 ucsz02 rxb80 txb80 164 / 174 (0xc0) ucsr0a rxc0 txc0 udre0 fe0 dor0 upe0 u2x0 mpcm0 163 / 173 (0xbf) reserved - - - - - - - - (0xbe) reserved - - - - - - - - 30. register summary (continued) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page notes: 1. for compatibility with future devices, reserved bits s hould be written to zero if accessed. reserved i/o memory addresses should never be written. 2. i/o registers within the address range $00 - $1f are directly bit-accessible using the sbi and cbi instructions. in these registers, the value of single bits can be checked by using the sbis and sbic instructions. 3. some of the status flags are cleared by writing a logical o ne to them. note that the cbi and sbi instructions will operate on all bits in the i/o register, writing a one back into any flag read as set, thus clearing the flag. the cbi and sbi instructions work with registers 0x00 to 0x1f only. 4. when using the i/o specific commands in and out, t he i/o addresses $00 - $3f must be used. when addressing i/o registers as data space using ld and st instructions, $20 must be added to these addresses. the atmega164p-b/324p-b/644p-b is a complex microcontro ller with more peripheral units than can be supported within the 64 location reserved in opcode for the in and ou t instructions. for the extended i/o space from $60 - $ff, only the st/sts/std and ld/lds/ldd instructions can be used. 5. usart in spi master mode. 325 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 (0xbd) twamr twam6 twam5 twam4 twam3 twam2 twam1 twam0 - 203 (0xbc) twcr twint twea twsta twsto twwc twen -twie 200 (0xbb) twdr 2-wire serial interface data register 202 (0xba) twar twa6 twa5 twa4 twa3 twa2 twa1 twa0 twgce 203 (0xb9) twsr tws7 tws6 tws5 tws4 tws3 - twps1 twps0 202 (0xb8) twbr 2-wire serial interface bit rate register 200 (0xb7) reserved - - - - - - - - (0xb6) assr - exclk as2 tcn2ub ocr2ab ocr2bub tcr2aub tcr2bb 136 (0xb5) reserved - - - - - - - - (0xb4) ocr2b timer/counter2 output compare register b 136 (0xb3) ocr2a timer/counter2 output compare register a 136 (0xb2) tcnt2 timer/counter2 (8 bit) 136 (0xb1) tccr2b foc2a foc2b - - wgm22 cs22 cs21 cs20 135 (0xb0) tccr2a com2a1 com2a0 com2b1 com2b0 - -wgm21wgm20 132 (0xaf) reserved - - - - - - - - (0xae) reserved - - - - - - - - (0xad) reserved - - - - - - - - (0xac) reserved - - - - - - - - (0xab) reserved - - - - - - - - (0xaa) reserved - - - - - - - - (0xa9) reserved - - - - - - - - (0xa8) reserved - - - - - - - - (0xa7) reserved - - - - - - - - (0xa6) reserved - - - - - - - - (0xa5) reserved - - - - - - - - (0xa4) reserved - - - - - - - - (0xa3) reserved - - - - - - - - (0xa2) reserved - - - - - - - - (0xa1) reserved - - - - - - - - (0xa0) reserved - - - - - - - - (0x9f) reserved - - - - - - - - (0x9e) reserved - - - - - - - - (0x9d) reserved - - - - - - - - (0x9c) reserved - - - - - - - - (0x9b) ocr3bh timer/counter3 - output compare register b high byte 114 (0x9a) ocr3bl timer/counter3 - output compare register b low byte 114 30. register summary (continued) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page notes: 1. for compatibility with future devices, reserved bits s hould be written to zero if accessed. reserved i/o memory addresses should never be written. 2. i/o registers within the address range $00 - $1f are directly bit-accessible using the sbi and cbi instructions. in these registers, the value of single bits can be checked by using the sbis and sbic instructions. 3. some of the status flags are cleared by writing a logical o ne to them. note that the cbi and sbi instructions will operate on all bits in the i/o register, writing a one back into any flag read as set, thus clearing the flag. the cbi and sbi instructions work with registers 0x00 to 0x1f only. 4. when using the i/o specific commands in and out, t he i/o addresses $00 - $3f must be used. when addressing i/o registers as data space using ld and st instructions, $20 must be added to these addresses. the atmega164p-b/324p-b/644p-b is a complex microcontro ller with more peripheral units than can be supported within the 64 location reserved in opcode for the in and ou t instructions. for the extended i/o space from $60 - $ff, only the st/sts/std and ld/lds/ldd instructions can be used. 5. usart in spi master mode. atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 326 (0x99) ocr3ah timer/counter3 - output compare register a high byte 113 (0x98) ocr3al timer/counter3 - output compare register a low byte 113 (0x97) icr3h timer/counter3 - input capture register high byte 114 (0x96) icr3l timer/counter3 - input capture register low byte 114 (0x95) tcnt3h timer/counter3 - counter register high byte 113 (0x94) tcnt3l timer/counter3 - counter register low byte 113 (0x93) reserved - - - - - - - - (0x92) tccr3c foc3a foc3b - - - - - - 112 (0x91) tccr3b icnc3 ices3 - wgm33 wgm32 cs32 cs31 cs30 111 (0x90) tccr3a com3a1 com3a0 com3b1 com3b0 - -wgm31wgm30 109 (0x8f) reserved - - - - - - - - (0x8e) reserved - - - - - - - - (0x8d) reserved - - - - - - - - (0x8c) reserved - - - - - - - - (0x8b) ocr1bh timer/counter1 - output compare register b high byte 114 (0x8a) ocr1bl timer/counter1 - output compare register b low byte 114 (0x89) ocr1ah timer/counter1 - output compare register a high byte 113 (0x88) ocr1al timer/counter1 - output compare register a low byte 113 (0x87) icr1h timer/counter1 - input capture register high byte 114 (0x86) icr1l timer/counter1 - input capture register low byte 114 (0x85) tcnt1h timer/counter1 - counter register high byte 113 (0x84) tcnt1l timer/counter1 - counter register low byte 113 (0x83) reserved - - - - - - - - (0x82) tccr1c foc1a foc1b - - - - - - 112 (0x81) tccr1b icnc1 ices1 - wgm13 wgm12 cs12 cs11 cs10 111 (0x80) tccr1a com1a1 com1a0 com1b1 com1b0 - -wgm11wgm10 109 (0x7f) didr1 - - - - - -ain1dain0d 206 (0x7e) didr0 adc7d adc6d adc5d adc4d adc3d adc2d adc1d adc0d 224 (0x7d) reserved - - - - - - - - (0x7c) admux refs1 refs0 adlar mux4 mux3 mux2 mux1 mux0 220 (0x7b) adcsrb -acme - - - adts2 adts1 adts0 205 (0x7a) adcsra aden adsc adate adif adie adps2 adps1 adps0 222 (0x79) adch adc data register high byte 223 (0x78) adcl adc data register low byte 223 (0x77) reserved - - - - - - - - (0x76) reserved - - - - - - - - 30. register summary (continued) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page notes: 1. for compatibility with future devices, reserved bits s hould be written to zero if accessed. reserved i/o memory addresses should never be written. 2. i/o registers within the address range $00 - $1f are directly bit-accessible using the sbi and cbi instructions. in these registers, the value of single bits can be checked by using the sbis and sbic instructions. 3. some of the status flags are cleared by writing a logical o ne to them. note that the cbi and sbi instructions will operate on all bits in the i/o register, writing a one back into any flag read as set, thus clearing the flag. the cbi and sbi instructions work with registers 0x00 to 0x1f only. 4. when using the i/o specific commands in and out, t he i/o addresses $00 - $3f must be used. when addressing i/o registers as data space using ld and st instructions, $20 must be added to these addresses. the atmega164p-b/324p-b/644p-b is a complex microcontro ller with more peripheral units than can be supported within the 64 location reserved in opcode for the in and ou t instructions. for the extended i/o space from $60 - $ff, only the st/sts/std and ld/lds/ldd instructions can be used. 5. usart in spi master mode. 327 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 (0x75) reserved - - - - - - - - (0x74) reserved - - - - - - - - (0x73) pcmsk3 pcint31 pcint30 pcint29 p cint28 pcint27 pcint26 pcint25 pcint24 55 (0x72) reserved - - - - - - - - (0x71) timsk3 - -icie3 - - ocie3b ocie3a toie3 116 (0x70) timsk2 - - - - - ocie2b ocie2a toie2 137 (0x6f) timsk1 - -icie1 - - ocie1b ocie1a toie1 115 (0x6e) timsk0 - - - - - ocie0b ocie0a toie0 89 (0x6d) pcmsk2 pcint23 pcint22 pcint21 pcint20 pcint19 pcint18 pcint17 pcint16 56 (0x6c) pcmsk1 pcint15 pcint14 pcint13 p cint12 pcint11 pcint10 pcint9 pcint8 56 (0x6b) pcmsk0 pcint7 pcint6 pcint5 pcint4 pcint3 pcint2 pcint1 pcint0 56 (0x6a) reserved - - - - - - - - (0x69) eicra - - isc21 isc20 isc11 isc10 isc01 isc00 53 (0x68) pcicr - - - - pcie3 pcie2 pcie1 pcie0 54 (0x67) reserved - - - - - - - - (0x66) osccal oscillator calibration register 32 (0x65) reserved - - - - - - - - (0x64) prr prtwi prtim2 prtim0 prusart1 prtim1 prspi prusart0 pradc 39 (0x63) reserved - - - - - - - - (0x62) reserved - - - - - - - - (0x61) clkpr clkpce - - - clkps3 clkps2 clkps1 clkps0 32 (0x60) wdtcsr wdif wdie wdp3 wdce wde wdp2 wdp1 wdp0 47 0x3f (0x5f) sreg i t h s v n z c 10 0x3e (0x5e) sph sp15 sp14 sp13 sp12 sp11 sp10 sp9 sp8 10 0x3d (0x5d) spl sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 10 0x3c (0x5c) reserved - - - - - - - - 0x3b (0x5b) reserved - - - - - - - - 0x3a (0x5a) reserved - - - - - - - - 0x39 (0x59) reserved - - - - - - - - 0x38 (0x58) reserved - - - - - - - - 30. register summary (continued) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page notes: 1. for compatibility with future devices, reserved bits s hould be written to zero if accessed. reserved i/o memory addresses should never be written. 2. i/o registers within the address range $00 - $1f are directly bit-accessible using the sbi and cbi instructions. in these registers, the value of single bits can be checked by using the sbis and sbic instructions. 3. some of the status flags are cleared by writing a logical o ne to them. note that the cbi and sbi instructions will operate on all bits in the i/o register, writing a one back into any flag read as set, thus clearing the flag. the cbi and sbi instructions work with registers 0x00 to 0x1f only. 4. when using the i/o specific commands in and out, t he i/o addresses $00 - $3f must be used. when addressing i/o registers as data space using ld and st instructions, $20 must be added to these addresses. the atmega164p-b/324p-b/644p-b is a complex microcontro ller with more peripheral units than can be supported within the 64 location reserved in opcode for the in and ou t instructions. for the extended i/o space from $60 - $ff, only the st/sts/std and ld/lds/ldd instructions can be used. 5. usart in spi master mode. atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 328 0x37 (0x57) spmcsr spmie rwwsb sigrd rwwsre blbset pgwrt pgers spmen 253 0x36 (0x56) reserved - - - - - - - - 0x35 (0x55) mcucr jtd bods bodse pud - - ivsel ivce 72 / 239 0x34 (0x54) mcusr - - - jtrf wdrf borf extrf porf 47 / 239 0x33 (0x53) smcr - - - - sm2 sm1 sm0 se 38 0x32 (0x52) reserved - - - - - - - - 0x31 (0x51) ocdr on-chip debug register 230 0x30 (0x50) acsr acd acbg aco aci acie acic acis1 acis0 222 0x2f (0x4f) reserved - - - - - - - - 0x2e (0x4e) spdr spi 0 data register 146 0x2d (0x4d) spsr spif0 wcol0 - - - - - spi2x0 145 0x2c (0x4c) spcr spie0 spe0 dord0 mstr0 cpol0 cpha0 spr01 spr00 144 0x2b (0x4b) gpior2 general purpose i/o register 2 22 0x2a (0x4a) gpior1 general purpose i/o register 1 22 0x29 (0x49) reserved - - - - - - - - 0x28 (0x48) ocr0b timer/counter0 output compare register b 88 0x27 (0x47) ocr0a timer/counter0 output compare register a 88 0x26 (0x46) tcnt0 timer/counter0 (8 bit) 88 0x25 (0x45) tccr0b foc0a foc0b - - wgm02 cs02 cs01 cs00 87 0x24 (0x44) tccr0a com0a1 com0a0 com0b1 com0b0 - -wgm01wgm00 88 30. register summary (continued) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page notes: 1. for compatibility with future devices, reserved bits s hould be written to zero if accessed. reserved i/o memory addresses should never be written. 2. i/o registers within the address range $00 - $1f are directly bit-accessible using the sbi and cbi instructions. in these registers, the value of single bits can be checked by using the sbis and sbic instructions. 3. some of the status flags are cleared by writing a logical o ne to them. note that the cbi and sbi instructions will operate on all bits in the i/o register, writing a one back into any flag read as set, thus clearing the flag. the cbi and sbi instructions work with registers 0x00 to 0x1f only. 4. when using the i/o specific commands in and out, t he i/o addresses $00 - $3f must be used. when addressing i/o registers as data space using ld and st instructions, $20 must be added to these addresses. the atmega164p-b/324p-b/644p-b is a complex microcontro ller with more peripheral units than can be supported within the 64 location reserved in opcode for the in and ou t instructions. for the extended i/o space from $60 - $ff, only the st/sts/std and ld/lds/ldd instructions can be used. 5. usart in spi master mode. 329 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 0x23 (0x43) gtccr tsm - - - - - psrasy psrsyn c 138 0x22 (0x42) eearh - - - - eeprom address register high byte 19 0x21 (0x41) eearl eeprom address register low byte 19 0x20 (0x40) eedr eeprom data register 19 0x1f (0x3f) eecr - - eepm1 eepm0 eerie eempe eepe eere 19 0x1e (0x3e) gpior0 general purpose i/o register 0 22 0x1d (0x3d) eimsk - - - - - int2 int1 int0 54 0x1c (0x3c) eifr - - - - - intf2 intf1 intf0 54 0x1b (0x3b) pcifr - - - - pcif3 pcif2 pcif1 pcif0 55 0x1a (0x3a) reserved - - - - - - - - 0x19 (0x39) reserved - - - - - - - - 0x18 (0x38) tifr3 - -icf3 - - ocf3b ocf3a tov3 118 0x17 (0x37) tifr2 - - - - - ocf2b ocf2a tov2 138 0x16 (0x36) tifr1 - -icf1 - - ocf1b ocf1a tov1 117 0x15 (0x35) tifr0 - - - - - ocf0b ocf0a tov0 89 0x14 (0x34) reserved - - - - - - - - 0x13 (0x33) reserved - - - - - - - - 0x12 (0x32) reserved - - - - - - - - 0x11 (0x31) reserved - - - - - - - - 0x10 (0x30) reserved - - - - - - - - 30. register summary (continued) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page notes: 1. for compatibility with future devices, reserved bits s hould be written to zero if accessed. reserved i/o memory addresses should never be written. 2. i/o registers within the address range $00 - $1f are directly bit-accessible using the sbi and cbi instructions. in these registers, the value of single bits can be checked by using the sbis and sbic instructions. 3. some of the status flags are cleared by writing a logical o ne to them. note that the cbi and sbi instructions will operate on all bits in the i/o register, writing a one back into any flag read as set, thus clearing the flag. the cbi and sbi instructions work with registers 0x00 to 0x1f only. 4. when using the i/o specific commands in and out, t he i/o addresses $00 - $3f must be used. when addressing i/o registers as data space using ld and st instructions, $20 must be added to these addresses. the atmega164p-b/324p-b/644p-b is a complex microcontro ller with more peripheral units than can be supported within the 64 location reserved in opcode for the in and ou t instructions. for the extended i/o space from $60 - $ff, only the st/sts/std and ld/lds/ldd instructions can be used. 5. usart in spi master mode. atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 330 0x0f (0x2f) reserved - - - - - - - - 0x0e (0x2e) reserved - - - - - - - - 0x0d (0x2d) reserved - - - - - - - - 0x0c (0x2c) reserved - - - - - - - - 0x0b (0x2b) portd portd7 portd6 portd5 portd4 portd3 portd2 portd1 portd0 74 0x0a (0x2a) ddrd ddd7 ddd6 ddd5 ddd4 ddd3 ddd2 ddd1 ddd0 74 0x09 (0x29) pind pind7 pind6 pind5 pind4 pind3 pind2 pind1 pind0 74 0x08 (0x28) portc portc7 portc6 portc5 portc4 portc3 portc2 portc1 portc0 73 0x07 (0x27) ddrc ddc7 ddc6 ddc5 ddc4 ddc3 ddc2 ddc1 ddc0 74 0x06 (0x26) pinc pinc7 pinc6 pinc5 pinc4 pinc3 pinc2 pinc1 pinc0 74 0x05 (0x25) portb portb7 portb6 portb5 portb4 portb3 portb2 portb1 portb0 73 0x04 (0x24) ddrb ddb7 ddb6 ddb5 ddb4 ddb3 ddb2 ddb1 ddb0 73 0x03 (0x23) pinb pinb7 pinb6 pinb5 pinb4 pinb3 pinb2 pinb1 pinb0 73 0x02 (0x22) porta porta7 porta6 porta5 porta4 porta3 porta2 porta1 porta0 73 0x01 (0x21) ddra dda7 dda6 dda5 dda4 dda3 dda2 dda1 dda0 73 0x00 (0x20) pina pina7 pina6 pina5 pina4 pina3 pina2 pina1 pina0 73 30. register summary (continued) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page notes: 1. for compatibility with future devices, reserved bits s hould be written to zero if accessed. reserved i/o memory addresses should never be written. 2. i/o registers within the address range $00 - $1f are directly bit-accessible using the sbi and cbi instructions. in these registers, the value of single bits can be checked by using the sbis and sbic instructions. 3. some of the status flags are cleared by writing a logical o ne to them. note that the cbi and sbi instructions will operate on all bits in the i/o register, writing a one back into any flag read as set, thus clearing the flag. the cbi and sbi instructions work with registers 0x00 to 0x1f only. 4. when using the i/o specific commands in and out, t he i/o addresses $00 - $3f must be used. when addressing i/o registers as data space using ld and st instructions, $20 must be added to these addresses. the atmega164p-b/324p-b/644p-b is a complex microcontro ller with more peripheral units than can be supported within the 64 location reserved in opcode for the in and ou t instructions. for the extended i/o space from $60 - $ff, only the st/sts/std and ld/lds/ldd instructions can be used. 5. usart in spi master mode. 331 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 31. instruction set summary mnemonics operands description operation flags #clocks arithmetic and logic instructions add rd, rr add two registers rd rd + rr z,c,n,v,h 1 adc rd, rr add with carry two registers rd rd + rr + c z,c,n,v,h 1 adiw rdl,k add immediate to word rdh: rdl rdh: rdl + k z,c,n,v,s 2 sub rd, rr subtract two registers rd rd ? rr z,c,n,v,h 1 subi rd, k subtract constant from register rd rd ? k z,c,n,v,h 1 sbc rd, rr subtract with carry two registers rd rd ? rr ? c z,c,n,v,h 1 sbci rd, k subtract with carry constant from reg. rd rd ? k ? c z,c,n,v,h 1 sbiw rdl,k subtract immediate from word rdh: rdl rdh: rdl ? k z,c,n,v,s 2 and rd, rr logical and registers rd rd rr z,n,v 1 andi rd, k logical and register and constant rd rd k z,n,v 1 or rd, rr logical or registers rd rd v rr z,n,v 1 ori rd, k logical or register and constant rd rd v k z,n,v 1 eor rd, rr exclusive or registers rd rd rr z,n,v 1 com rd one?s complement rd 0xff ? rd z,c,n,v 1 neg rd two?s complement rd 0x00 ? rd z,c,n,v,h 1 sbr rd,k set bit(s) in register rd rd v k z,n,v 1 cbr rd,k clear bit(s) in register rd rd (0xff ? k) z,n,v 1 inc rd increment rd rd + 1 z,n,v 1 dec rd decrement rd rd ? 1 z,n,v 1 tst rd test for zero or minus rd rd rd z,n,v 1 clr rd clear register rd rd rd z,n,v 1 ser rd set register rd 0xff none 1 mul rd, rr multiply unsigned r1:r0 rd x rr z,c 2 muls rd, rr multiply signed r1:r0 rd x rr z,c 2 mulsu rd, rr multiply signed with unsigned r1:r0 rd x rr z,c 2 fmul rd, rr fractional multiply unsigned r1:r0 (rd x rr) << 1 z,c 2 fmuls rd, rr fractional multiply signed r1:r0 (rd x rr) << 1 z,c 2 fmulsu rd, rr fractional multiply signed with unsigned r1:r0 (rd x rr) << 1 z,c 2 branch instructions rjmp k relative jump pc pc + k + 1 none 2 ijmp indirect jump to (z) pc z none 2 jmp k direct jump pc k none 3 rcall k relative subroutine call pc pc + k + 1 none 4 icall indirect call to (z) pc z none 4 call k direct subroutine call pc k none 5 ret subroutine return pc stack none 5 reti interrupt return pc stack i 5 cpse rd, rr compare, skip if equal if (rd = rr) pc pc + 2 or 3 none 1/2/3 cp rd, rr compare rd ? rr z,n,v,c,h 1 cpc rd, rr compare with carry rd ? rr ? c z,n,v,c,h 1 cpi rd, k compare register with immediate rd ? k z,n,v,c,h 1 atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 332 sbrc rr, b skip if bit in register cleared if (rr(b)=0) pc pc + 2 or 3 none 1/2/3 sbrs rr, b skip if bit in register is set if (rr(b)=1) pc pc + 2 or 3 none 1/2/3 sbic p, b skip if bit in i/o register cleared if (p(b)=0) pc pc + 2 or 3 none 1/2/3 sbis p, b skip if bit in i/o register is set if (p(b)=1) pc pc + 2 or 3 none 1/2/3 brbs s, k branch if status flag set if (sreg (s) = 1) then pc pc + k + 1 none 1/2 brbc s, k branch if status flag cleared if (sreg (s) = 0) then pc pc + k + 1 none 1/2 breq k branch if equal if (z = 1) then pc pc + k + 1 none 1/2 brne k branch if not equal if (z = 0) then pc pc + k + 1 none 1/2 brcs k branch if carry set if (c = 1) then pc pc + k + 1 none 1/2 brcc k branch if carry cleared if (c = 0) then pc pc + k + 1 none 1/2 brsh k branch if same or higher if (c = 0) then pc pc + k + 1 none 1/2 brlo k branch if lower if (c = 1) then pc pc + k + 1 none 1/2 brmi k branch if minus if (n = 1) then pc pc + k + 1 none 1/2 brpl k branch if plus if (n = 0) then pc pc + k + 1 none 1/2 brge k branch if greater or equal, signed if (n v= 0) then pc pc + k + 1 none 1/2 brlt k branch if less than zero, signed if (n v= 1) then pc pc + k + 1 none 1/2 brhs k branch if half carry flag set if (h = 1) then pc pc + k + 1 none 1/2 brhc k branch if half carry flag cleared if (h = 0) then pc pc + k + 1 none 1/2 brts k branch if t flag set if (t = 1) then pc pc + k + 1 none 1/2 brtc k branch if t flag cleared if (t = 0) then pc pc + k + 1 none 1/2 brvs k branch if overflow flag is set if (v = 1) then pc pc + k + 1 none 1/2 brvc k branch if overflow flag is cleared if (v = 0) then pc pc + k + 1 none 1/2 brie k branch if interrupt enabled if (i = 1) then pc pc + k + 1 none 1/2 brid k branch if interrupt disabled if (i = 0) then pc pc + k + 1 none 1/2 bit and bit-test instructions sbi p, b set bit in i/o register i/o (p, b) 1 none 2 cbi p, b clear bit in i/o register i/o (p, b) 0 none 2 lsl rd logical shift left rd(n+1) rd (n), rd(0) 0 z,c,n,v 1 lsr rd logical shift right rd (n) rd(n+1), rd(7) 0 z,c,n,v 1 rol rd rotate left through carry rd(0) c,rd(n+1) rd (n), c rd(7) z,c,n,v 1 ror rd rotate right through carry rd(7) c, rd (n) rd(n+1),c rd(0) z,c,n,v 1 asr rd arithmetic shift right rd (n) rd(n+1), n=0..6 z,c,n,v 1 swap rd swap nibbles rd(3..0) rd(7..4),rd(7..4) rd(3..0) none 1 bset s flag set sreg (s) 1 sreg (s) 1 bclr s flag clear sreg (s) 0 sreg (s) 1 bst rr, b bit store from register to t t rr (b) t 1 bld rd, b bit load from t to register rd (b) t none 1 sec set carry c 1 c 1 clc clear carry c 0 c 1 sen set negative flag n 1 n 1 cln clear negative flag n 0 n 1 sez set zero flag z 1 z 1 31. instruction set summary (continued) mnemonics operands description operation flags #clocks 333 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 clz clear zero flag z 0 z 1 sei global interrupt enable i 1 i 1 cli global interrupt disable i 0 i 1 ses set signed test flag s 1 s 1 cls clear signed test flag s 0 s 1 sev set twos complement overflow. v 1 v 1 clv clear twos complement overflow v 0 v 1 set set t in sreg t 1 t 1 clt clear t in sreg t 0 t 1 seh set half carry flag in sreg h 1 h 1 clh clear half carry flag in sreg h 0 h 1 data transfer instructions mov rd, rr move between registers rd rr none 1 movw rd, rr copy register word rd+1:rd rr+1:rr none 1 ldi rd, k load immediate rd k none 1 ld rd, x load indirect rd (x) none 2 ld rd, x+ load indirect and post-inc. rd (x), x x + 1 none 2 ld rd, - x load indirect and pre-dec. x x ? 1, rd (x) none 2 ld rd, y load indirect rd (y) none 2 ld rd, y+ load indirect and post-inc. rd (y), y y + 1 none 2 ld rd, -y load indirect and pre-dec. y y ? 1, rd (y) none 2 ldd rd, y+q load indirect with displacement rd (y + q) none 2 ld rd, z load indirect rd (z) none 2 ld rd, z+ load indirect and post-inc. rd (z), z z+1 none 2 ld rd, -z load indirect and pre-dec. z z - 1, rd (z) none 2 ldd rd, z+q load indirect with displacement rd (z + q) none 2 lds rd, k load direct from sram rd (k) none 2 st x, rr store indirect (x) rr none 2 st x+, rr store indirect and post-inc. (x) rr, x x + 1 none 2 st -x, rr store indirect and pre-dec. x x ? 1, (x) rr none 2 st y, r r store indirect (y) rr none 2 st y+, rr store indirect and post-inc. (y) rr, y y + 1 none 2 st -y, rr store indirect and pre-dec. y y ? 1, (y) rr none 2 std y+q, rr store indirect with displacement (y + q) rr none 2 st z, rr store indirect (z) rr none 2 st z+, rr store indirect and post-inc. (z) rr, z z + 1 none 2 st -z, rr store indirect and pre-dec. z z ? 1, (z) rr none 2 std z+q, rr store indirect with displacement (z + q) rr none 2 sts k, rr store direct to sram (k) rr none 2 lpm load program memory r0 (z) none 3 lpm rd, z load program memory rd (z) none 3 lpm rd, z+ load program memory and post-inc rd (z), z z+1 none 3 31. instruction set summary (continued) mnemonics operands description operation flags #clocks atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 334 spm store program memory (z) r1:r0 none - in rd, p in port rd p none 1 out p, r r out port p rr none 1 push rr push register on stack stack rr none 2 pop rd pop register from stack rd stack none 2 mcu control instructions nop no operation none 1 sleep sleep (see specific descr. for sleep function) none 1 wdr watchdog reset (see specific descr. for wdr/timer) none 1 break break for on-chip debug only none n/a 31. instruction set summary (continued) mnemonics operands description operation flags #clocks 335 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 33. packaging information 32. ordering information speed (mhz) (3) power supply ordering code (2) package (1) operational range 16 2.7 ? 5.5v atmega164p-b15az atmega164p-b15mz atmega324p-b15az atmega324p-b15mz atmega644p-b15az atmega644p-b15mz ml pw ml pw ml pw automotive (?40 o c to 125 o c) notes: 1. this device can also be supplied in wafer form. please c ontact your local atmel sales office for detailed ordering info r- mation and minimum quantities. 2. pb-free packaging, complies to the european directive for re striction of hazardous substa nces (rohs directive). also halide free and fully green. 3. for speed versus v cc see section 28.3 ?speed grades? on page 289 . table 33-1. package types package type ml 44-lead, thin (1.0mm) plastic gu ll wing quad flat package (tqfp) pw 44-pad, 7 x 7 x 1.0mm body, lead pitch 0.50mm, quad flat no-lead/micro lead frame package (qfn/mlf) atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 336 figure 33-1. ml package drawing contact: packagedrawings@atmel.com gpc drawing no. rev. title ml aix i 02/28/12 ml, 44 lds - 0.80mm pitch, 10x10x1.00mm body size thin profile plastic quad flat package (tqfp) d1 d e drawings not scaled e1 c 0 ~ 7 l 44 1. notes: 2. 3. this drawing is for general information only. refer to jedec drawing ms-026, variation acb. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25mm per side. dimensions d1 and e1 are maximum plastic body size dimensions including mold mismatch. lead coplanarity is 0.10mm maximum. a a2 a1 e b common dimensions (unit of measure = mm) min nom note max symbol 0.15 0.05 a1 0.20 0.09 c 0.80 typ. e 44 n 0.45 0.30 b 0.75 0.45 l 10.10 9.90 10.00 d1/e1 12.00 12.25 11.75 d/e 1.00 1.05 0.95 a2 1.20 a 2 top view side view bottom view 337 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 figure 33-2. pw package drawing contact: packagedrawings@atmel.com gpc drawing no. rev. title pw zcp h 02/17/12 pw, 44 leads - 0.50mm pitch, 7x7x1mm body size very thin quad flat package (punched) (vqfn) sawn d2 e2 1 2 3 pin# 1 corner option a option b pin 1# chamfer (c 0.30) pin 1# triangle pin 1# notch (c 0.20 r) l k k be d e 1. notes: 2. this drawing is for general information only. refer to jedec drawing mo-220, variation vkkd-1, for proper dimensions, tolerance s, datums, etc. dimensions b applies to metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. if the terminal has the optical radius on the other end of the terminal, the dimensions should not be measured in that radius a rea. marked pin# 1d a a3 a1 0.08 seating plane drawings not scaled top view side view bottom view option c common dimensions (unit of measure = mm) min nom note max symbol 0.05 0.80 a1 0.02 0.65 0.45 0.55 l 0.50 bsc e 44 n 0.30 2 0.18 0.23 b 0.35 k 5.40 5.00 5.20 d2/e2 7.00 7.10 6.90 d/e 0.20 ref a3 1.00 a atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 338 34. errata 34.1 errata for atmega164p-b 34.1.1 rev. e no known errata. 34.2 errata for atmega324p-b 34.2.1 rev. f no known errata. 34.3 errata for atmega644p-b 34.3.1 rev. g no known errata. 35. revision history please note that the following page numbers re ferred to in this section re fer to the specific revision mentioned, not to this document. revision no. history 9255e-avr-08/14 ? put datasheet in the latest template 339 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 36. table of contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1. pin configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 pinout - tqfp/qfn/mlf for atmega164p-b/324p-b/644p-b . . . . . . . . . . . . . . . . . . . . . . . . 3 2. overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.2 automotive quality grade . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.3 comparison between atmega164p-b, atmega324p-b and atmega644p-b. . . . . . . . . . . . 5 2.4 pin descriptions 6 3. resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4. about code examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5. data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6. capacitive touch sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 7. avr cpu core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 7.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 7.2 alu ? arithmetic logic unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 7.3 status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 7.4 general purpose register file. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 7.5 stack pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7.6 instruction execution timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7.7 reset and interrupt handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 8. avr memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6 8.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 8.2 in-system reprogrammable flash program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 8.3 sram data memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 8.4 eeprom data memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8.5 i/o memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8.6 register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 9. system clock and clock options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 9.1 clock systems and their distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 9.2 clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 9.3 low power crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 9.4 full swing crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 9.5 low frequency crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 8 9.6 calibrated internal rc oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 9.7 128khz internal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 9.8 external clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 9.9 timer/counter oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 9.10 clock output buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 9.11 system clock prescaler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 9.12 register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 10. power management and sleep modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 10.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 10.2 sleep modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 10.3 bod disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 10.4 idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 10.5 adc noise reduction mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 340 10.6 power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 10.7 power-save mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 10.8 standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 10.9 extended standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 10.10 power reduction register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 10.11 minimizing power consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 10.12 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 11. system control and reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 11.1 resetting the avr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 11.2 internal voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 11.3 watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 11.4 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 12. interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 12.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 12.2 interrupt vectors in atmega164p-b/324p-b/644p-b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 12.3 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 13. external interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 13.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 13.2 register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 14. i/o-ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 14.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 14.2 ports as general digital i/o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 14.3 alternate port functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 14.4 register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 15. 8-bit timer/counter0 with pwm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 15.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 15.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 15.3 timer/counter clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 15.4 counter unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 15.5 output compare unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 15.6 compare match output unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 15.7 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 15.8 timer/counter timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 15.9 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 16. 16-bit timer/counter1 and timer/counter3 with pwm . . . . . . . . . . . . . . . . . . . . . . . . . 90 16.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 16.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 16.3 accessing 16-bit registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 16.4 timer/counter clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 16.5 counter unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 16.6 input capture unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 16.7 output compare units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 16.8 compare match output unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 00 16.9 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 16.10 timer/counter timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 7 16.11 register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 17. 8-bit timer/counter2 with pwm and asynchronous operation . . . . . . . . . . . . . . . . . 119 17.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 17.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 17.3 timer/counter clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 21 341 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 17.4 counter unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 17.5 output compare unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 17.6 compare match output unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 24 17.7 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 17.8 timer/counter timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 17.9 asynchronous operation of timer/counter2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 17.10 timer/counter prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 17.11 register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 18. spi ? serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 18.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 18.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 18.3 ss pin functionality. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 18.4 data modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 18.5 register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 19. usart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 19.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 19.2 usart1 and usart0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 19.3 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 19.4 clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 19.5 frame formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 19.6 usart initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 19.7 data transmission ? the usart transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 19.8 data reception ? the usart receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 19.9 asynchronous data reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 19.10 multi-processor communication mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 19.11 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 19.12 examples of baud rate setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 66 20. usart in spi mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 20.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 20.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 20.3 clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 20.4 spi data modes and timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 70 20.5 frame formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 20.6 data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 20.7 avr usart mspim versus avr spi. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 20.8 register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 21. two-wire serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 21.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 21.2 two-wire serial interface bus definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 21.3 data transfer and frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 21.4 multi-master bus systems, arbitration and synchronization . . . . . . . . . . . . . . . . . . . . . . . . 179 21.5 overview of the twi module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 21.6 using the twi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 21.7 transmission modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 21.8 multi-master systems and arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 21.9 register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 22. ac - analog comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 22.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 22.2 analog comparator multiplexed input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 22.3 register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 atmega164p-b/atmega324p-b/atmega644p-b [datasheet] 9255e?avr?08/14 342 23. adc - analog-to-digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 23.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 23.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 23.3 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 23.4 starting a conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 23.5 prescaling and conversion timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 23.6 changing channel or reference selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 23.7 adc noise canceler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 23.8 adc conversion result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 23.9 register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 24. jtag interface and on-chip debug system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 24.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 24.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 24.3 tap ? test access port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 24.4 tap controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 24.5 using the boundary-scan chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 24.6 using the on-chip debug system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 24.7 on-chip debug specific jtag instruct ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 24.8 using the jtag programming capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 24.9 bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 24.10 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 25. ieee 1149.1 (jtag) bo undary-scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 25.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 25.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 25.3 data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 25.4 boundary-scan specific jtag instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 25.5 boundary-scan chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 25.6 atmega164p-b/324p-b/644p-b boundary-scan order . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 25.7 boundary-scan description language files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 25.8 register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 26. boot loader support ? read-while-write self-pro gramming . . . . . . . . . . . . . . . . . . 240 26.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 26.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 26.3 application and boot loader flash se ctions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 26.4 read-while-write and no read-while-write flash sect ions . . . . . . . . . . . . . . . . . . . . . . . 241 26.5 boot loader lock bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 26.6 entering the boot loader program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 26.7 addressing the flash during self-programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 26.8 self-programming the flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 26.9 register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 27. memory programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 27.1 program and data memory lock bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 27.2 fuse bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 27.3 signature bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 27.4 calibration byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 27.5 page size. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 27.6 parallel programming parameters, pin mapping, and commands . . . . . . . . . . . . . . . . . . . 259 27.7 parallel programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 27.8 serial downloading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 27.9 serial programming instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2 27.10 programming via the jtag interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 343 atmega164p-b/atmega324p-b /atmega644p-b [datasheet] 9255e?avr?08/14 28. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 28.1 absolute maximum ratings* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 87 28.2 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 28.3 speed grades . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 28.4 clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 28.5 system and reset characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 28.6 external interrupts characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 28.7 spi timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 28.8 2-wire serial interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3 28.9 adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 29. typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 29.1 atmega164p-b typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 29.2 atmega324p-b typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 29.3 atmega644p-b typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 30. register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323 31. instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331 32. ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 33. packaging information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 34. errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338 34.1 errata for atmega164p-b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338 34.2 errata for atmega324p-b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338 34.3 errata for atmega644p-b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338 35. revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338 36. table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 39 x x xx x x atmel corporation 1600 technology drive, san jose, ca 95110 usa t: (+1)(408) 441.0311 f: (+1)(408) 436.4200 | www.atmel.com ? 2014 atmel corporation. / rev.: rev.: 9255e?avr?08/14 atmel ? , atmel logo and combinations thereof, enabling unlimited possibilities ? , avr ? , aks ? , qtouch ? , and others are registered trademarks or trademarks of atmel corporation in u.s. and other countries. windows ? is a registered trademark of microsoft corporation in u.s. and or other countries. other terms and product names may be trademarks of others. disclaimer: the information in this document is provided in c onnection with atmel products. no license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of atmel products. except as set forth in the atmel terms and condit ions of sales located on the atmel website, atmel assumes no liability wh atsoever and disclaims any express, implied or statutory warranty relating to its p roducts including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or non-infringement. in no event shall atmel be liable for any direct, indirect, consequential, pu nitive, special or incidental damages (including, without limi tation, damages for loss and profits, business interruption, or loss of information ) arising out of the use or inability to use this document, even if atmel has been advised of the possibility of such damages. atmel makes no r epresentations or warranties with respect to the accuracy or c ompleteness of the contents of this document and reserves the right to make changes to specificatio ns and products descriptions at any time without notice. atmel d oes not make any commitment to update the information contained herein. unless specifically provided otherwise, atme l products are not suitable for, and shall not be used in, automo tive applications. atmel products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. safety-critical, military, and automotive applications disclaim er: atmel products are not designed for and will not be used in connection with any applications where the failure of such products would reasonably be expected to re sult in significant personal inju ry or death (?safety-critical a pplications?) without an atmel officer's specific written consent. safety-critical applications incl ude, without limitation, life support devices and systems, equipment or systems for t he operation of nuclear facilities and weapons systems. atmel products are not designed nor intended for use in military or aerospace applications or environments unless specifically designated by atmel as military-grade. atmel products are not designed nor intended for use in automot ive applications unless spec ifically designated by atmel as automotive-grade. |
Price & Availability of ATMEGA324P-B-14
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |